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authorTristan Gingold <tgingold@free.fr>2017-06-09 06:27:13 +0200
committerTristan Gingold <tgingold@free.fr>2017-06-09 06:27:13 +0200
commit5ba7861a7d065b1feb90de890ce34e837cb12fdf (patch)
treec8124cb5be61171e751ebd3ef58570c3c6c58913 /testsuite/gna/issue283/Makefile
parentdeb8888cec67e91b834f97b16cb29774d63e9c68 (diff)
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Add (disabled) testcase for #283
Diffstat (limited to 'testsuite/gna/issue283/Makefile')
-rw-r--r--testsuite/gna/issue283/Makefile37
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/gna/issue283/Makefile b/testsuite/gna/issue283/Makefile
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+PWD=$(shell pwd)
+
+# Adjust to your needs:
+# ======================================================================================================================
+
+# Path to the root folder of the simulation framework
+SIM_FRAMEWORK_DIR = /home/kaolpr/simulation_framework
+
+# Top VHDL entity
+TOPLEVEL = foo
+
+# Python test file name (without extension)
+MODULE = example
+
+# Waveform output file
+WAVEFORM_OUTPUT = waveform.ghw
+
+# (Typically) Not to be modified:
+# ======================================================================================================================
+
+UNISIM_DIR = $(SIM_FRAMEWORK_DIR)/lib/xilinx-vivado/unisim/v08/
+VHDL_VERSION = 08
+
+VHDL_SOURCES = $(shell pwd)/bar.vhd $(shell pwd)/uut.vhd
+
+COCOTB = $(SIM_FRAMEWORK_DIR)/lib/cocotb
+GHDL_BIN_DIR = $(SIM_FRAMEWORK_DIR)/lib/ghdl/build/bin/
+
+SIM=ghdl
+ANALYSE_ARGS =
+ELABORATE_ARGS =
+SIM_ARGS = --wave=$(WAVEFORM_OUTPUT) --ieee-asserts=disable
+
+PYTHON_SIM_MODULES_PATH = $(SIM_FRAMEWORK_DIR)/lib/python_modules
+
+include $(COCOTB)/makefiles/Makefile.inc
+include $(COCOTB)/makefiles/Makefile.sim