Add (disabled) testcase for #283

6 files changed, 175 insertions, 0 deletions

diff --git a/testsuite/gna/issue283/Makefile b/testsuite/gna/issue283/Makefile
new file mode 100644
index 000000000..0dbcd4cbd
--- /dev/null
+++ b/testsuite/gna/issue283/Makefile
@@ -0,0 +1,37 @@
+PWD=$(shell pwd)
+
+# Adjust to your needs:
+# ======================================================================================================================
+
+# Path to the root folder of the simulation framework
+SIM_FRAMEWORK_DIR = /home/kaolpr/simulation_framework
+
+# Top VHDL entity
+TOPLEVEL = foo
+
+# Python test file name (without extension)
+MODULE = example
+
+# Waveform output file
+WAVEFORM_OUTPUT = waveform.ghw
+
+# (Typically) Not to be modified:
+# ======================================================================================================================
+
+UNISIM_DIR = $(SIM_FRAMEWORK_DIR)/lib/xilinx-vivado/unisim/v08/
+VHDL_VERSION = 08
+
+VHDL_SOURCES = $(shell pwd)/bar.vhd $(shell pwd)/uut.vhd
+
+COCOTB = $(SIM_FRAMEWORK_DIR)/lib/cocotb
+GHDL_BIN_DIR = $(SIM_FRAMEWORK_DIR)/lib/ghdl/build/bin/
+
+SIM=ghdl
+ANALYSE_ARGS =
+ELABORATE_ARGS =
+SIM_ARGS = --wave=$(WAVEFORM_OUTPUT) --ieee-asserts=disable
+
+PYTHON_SIM_MODULES_PATH = $(SIM_FRAMEWORK_DIR)/lib/python_modules
+
+include $(COCOTB)/makefiles/Makefile.inc
+include $(COCOTB)/makefiles/Makefile.sim
diff --git a/testsuite/gna/issue283/Makefile.ghdl b/testsuite/gna/issue283/Makefile.ghdl
new file mode 100644
index 000000000..f8804bfac
--- /dev/null
+++ b/testsuite/gna/issue283/Makefile.ghdl
@@ -0,0 +1,75 @@
+###############################################################################
+# Copyright (c) 2014 Potential Ventures Ltd
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Potential Ventures Ltd,
+#       SolarFlare Communications Inc nor the
+#       names of its contributors may be used to endorse or promote products
+#       derived from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+###############################################################################
+
+ifneq ($(VERILOG_SOURCES),)
+
+results.xml:
+	@echo "Skipping simulation as Verilog is not supported on simulator=$(SIM)"
+clean::
+
+else
+
+CMD_BIN := ghdl
+
+ifdef GHDL_BIN_DIR
+    CMD := $(shell which $(GHDL_BIN_DIR)/$(CMD_BIN) 2>/dev/null)
+else
+    # auto-detect bin dir from system path
+    CMD := $(shell which $(CMD_BIN) 2>/dev/null)
+endif
+
+ifeq (, $(CMD))
+    $(error "Unable to locate command >$(CMD_BIN)<")
+else
+	GHDL_BIN_DIR := $(shell dirname $(CMD))
+    export GHDL_BIN_DIR
+endif
+
+RTL_LIBRARY ?= work
+
+ifdef VHDL_VERSION
+	GHDL_STD = --std=$(VHDL_VERSION)
+endif
+
+.PHONY: analyse
+
+# Compilation phase
+analyse: $(VHDL_SOURCES) $(SIM_BUILD)
+	cd $(SIM_BUILD); \
+	$(CMD) -i $(GHDL_STD) --ieee=synopsys --mb-comments -fexplicit -frelaxed-rules --work=$(RTL_LIBRARY) -P$(UNISIM_DIR) $(VHDL_SOURCES); \
+	$(CMD) -m $(GHDL_STD) $(ELABORATE_ARGS) --ieee=synopsys -frelaxed-rules --work=$(RTL_LIBRARY) -P$(UNISIM_DIR) $(TOPLEVEL)
+
+results.xml: analyse  $(COCOTB_LIBS) $(COCOTB_VPI_LIB)
+	cd $(SIM_BUILD); \
+	PYTHONPATH=$(PYTHON_SIM_MODULES_PATH):$(LIB_DIR):$(SIM_ROOT):$(PWD):$(PYTHONPATH) LD_LIBRARY_PATH=$(GHDL_BIN_DIR)/../lib:$(LIB_DIR):$(LD_LIBRARY_PATH) MODULE=$(MODULE) \
+        TESTCASE=$(TESTCASE) TOPLEVEL=$(TOPLEVEL) TOPLEVEL_LANG=$(TOPLEVEL_LANG) \
+	$(CMD) -r --ieee=synopsys -frelaxed-rules -P$(UNISIM_DIR) $(GHDL_STD) $(TOPLEVEL) --vpi=$(LIB_DIR)/libvpi.$(LIB_EXT) $(SIM_ARGS)
+
+clean::
+	-@rm -rf $(SIM_BUILD)
+endif
diff --git a/testsuite/gna/issue283/bar.vhd b/testsuite/gna/issue283/bar.vhd
new file mode 100644
index 000000000..ca9c01b78
--- /dev/null
+++ b/testsuite/gna/issue283/bar.vhd
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity Bar is
+  port (
+    a : std_logic
+  );
+end entity Bar;
+
+architecture RTL of Bar is
+
+  signal s_test : std_logic_vector(3 downto 0) := "1111";
+
+begin
+
+end architecture;
diff --git a/testsuite/gna/issue283/example.py b/testsuite/gna/issue283/example.py
new file mode 100644
index 000000000..d4472dcb9
--- /dev/null
+++ b/testsuite/gna/issue283/example.py
@@ -0,0 +1,11 @@
+import cocotb
+from cocotb.triggers import Timer
+
+
+@cocotb.test()
+def test_transaction(dut):
+  
+    yield Timer(1)
+
+    dut._log.info("%d" % dut.s_test)
+    dut._log.info("%d" % dut.cmp_bar.s_test)
diff --git a/testsuite/gna/issue283/testsuite.sh b/testsuite/gna/issue283/testsuite.sh
new file mode 100755
index 000000000..13cf1d89c
--- /dev/null
+++ b/testsuite/gna/issue283/testsuite.sh
@@ -0,0 +1,5 @@
+#! /bin/sh
+
+# Need cocotb
+
+echo "Test skipped"
diff --git a/testsuite/gna/issue283/uut.vhd b/testsuite/gna/issue283/uut.vhd
new file mode 100644
index 000000000..ad3713dd8
--- /dev/null
+++ b/testsuite/gna/issue283/uut.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+entity foo is
+  port (
+    a : std_logic;
+    b : std_logic_vector(7 downto 0)
+  );
+end entity foo;
+
+architecture RTL of foo is
+
+  signal s_test : std_logic_vector(3 downto 0) := "1111";
+
+begin
+
+  cmp_bar: entity work.bar
+    port map(
+      a => a
+    );
+    
+  gen_bars: for i in 0 to 1 generate
+    cmp_generated_bar: entity work.bar
+      port map(
+        a => a
+      );
+  end generate gen_bars;
+
+end architecture;