testsuite/gna: add a test for #2336

1 files changed, 17 insertions, 0 deletions

diff --git a/testsuite/gna/issue2336/repro.vhdl b/testsuite/gna/issue2336/repro.vhdl
new file mode 100644
index 000000000..b0f6a6c90
--- /dev/null
+++ b/testsuite/gna/issue2336/repro.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro is
+  port (a, b, clk : std_logic);
+end;
+
+architecture behav of repro is
+begin
+  default clock is rising_edge(clk);
+
+   -- This assertion should hold, but doesn't (GHDL BUG)
+--  NEXT_0_a : assert always (a -> next_event_e(true)[2 to 2] (b));
+--    NEXT_1_a : assert always (a -> next_e[2 to 4] (b));
+--    NEXT_2_a : assert always (a -> {true[->2 to 3] : b});
+  NEXT_3_a : assert always (a -> {true[->2 to 3] ; b});
+end behav;