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authorTristan Gingold <tgingold@free.fr>2022-12-19 18:32:18 +0100
committerTristan Gingold <tgingold@free.fr>2022-12-19 18:32:18 +0100
commit6185c8d2de85828d53135433019968aa54699947 (patch)
treef76b1c42bd434223e6278374d137f6f20572b145 /testsuite/gna/issue2276/mwe.vhdl
parentc5b1522aec8cbb90167e0a7d7b04e73d6b96fa21 (diff)
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testsuite/gna: add a test for #2276
Diffstat (limited to 'testsuite/gna/issue2276/mwe.vhdl')
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diff --git a/testsuite/gna/issue2276/mwe.vhdl b/testsuite/gna/issue2276/mwe.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mwe is
+end entity;
+
+architecture tb of mwe is
+
+ constant ic_slv : std_logic_vector(63 downto 0) := x"7000000000000228";
+ signal ic_bv : bit_vector(ic_slv'range);
+
+begin
+
+ ic_bv <= to_bitvector(ic_slv);
+
+end architecture;