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author | Tristan Gingold <tgingold@free.fr> | 2022-10-10 18:20:39 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-10-10 18:20:39 +0200 |
commit | f2c863f7e030796cb325885654ffe3e945f35198 (patch) | |
tree | 319d452db49cb1e002265f5e9393f1a8d47e65f2 /testsuite/gna/issue2212/minimal.vhdl | |
parent | 5726f0eccf874b872ce0729aab42f587d915a3f5 (diff) | |
download | ghdl-f2c863f7e030796cb325885654ffe3e945f35198.tar.gz ghdl-f2c863f7e030796cb325885654ffe3e945f35198.tar.bz2 ghdl-f2c863f7e030796cb325885654ffe3e945f35198.zip |
testsuite/gna: add a test for #2212
Diffstat (limited to 'testsuite/gna/issue2212/minimal.vhdl')
-rw-r--r-- | testsuite/gna/issue2212/minimal.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/gna/issue2212/minimal.vhdl b/testsuite/gna/issue2212/minimal.vhdl new file mode 100644 index 000000000..82f034123 --- /dev/null +++ b/testsuite/gna/issue2212/minimal.vhdl @@ -0,0 +1,22 @@ +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + +entity minimal is + port( + duty_cycle: in std_logic_vector(7 downto 0) + ); +end entity minimal; + +architecture rtl of minimal is + +begin + + DECIDE_STATE: process(all) is +--DECIDE_STATE: process(duty_cycle) is -- uncomment to run + variable duty : boolean; + begin + duty := true when signed(duty_cycle) > 0 else false; + end process; + +end architecture rtl; |