testsuite/gna: add a test for #1914

1 files changed, 20 insertions, 0 deletions

diff --git a/testsuite/gna/issue1914/delayline1d.vhdl b/testsuite/gna/issue1914/delayline1d.vhdl
new file mode 100644
index 000000000..e5d79c01c
--- /dev/null
+++ b/testsuite/gna/issue1914/delayline1d.vhdl
@@ -0,0 +1,20 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity delayline1d is
+    generic (
+        delay : positive
+    );
+    port (
+        clk   : in std_logic;
+        i     : in std_logic;
+        o     : out std_logic
+    );
+end entity;
+
+architecture rtl of delayline1d is
+    signal d : std_logic_vector(delay - 1 downto 0);
+begin
+    (o, d) <= d & i when rising_edge(clk);
+
+end architecture rtl;