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author | Tristan Gingold <tgingold@free.fr> | 2020-02-01 17:18:13 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-01 17:18:13 +0100 |
commit | 5428d6e8537dbe4b9533a29b5d8124340471cb4c (patch) | |
tree | bf53450b2a0a1f512e777dff6e0def3848b01758 /testsuite/gna/issue1123 | |
parent | 6ed3a69222597c8660d8d9ad9da1e06c3d11474f (diff) | |
download | ghdl-5428d6e8537dbe4b9533a29b5d8124340471cb4c.tar.gz ghdl-5428d6e8537dbe4b9533a29b5d8124340471cb4c.tar.bz2 ghdl-5428d6e8537dbe4b9533a29b5d8124340471cb4c.zip |
testsuite/gna: add a test for #1123
Diffstat (limited to 'testsuite/gna/issue1123')
-rw-r--r-- | testsuite/gna/issue1123/b.vhdl | 32 | ||||
-rw-r--r-- | testsuite/gna/issue1123/b1.vhdl | 32 | ||||
-rwxr-xr-x | testsuite/gna/issue1123/testsuite.sh | 11 |
3 files changed, 75 insertions, 0 deletions
diff --git a/testsuite/gna/issue1123/b.vhdl b/testsuite/gna/issue1123/b.vhdl new file mode 100644 index 000000000..36e18b9e9 --- /dev/null +++ b/testsuite/gna/issue1123/b.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity A is +port(x: in std_ulogic_vector(4 downto 0)); +end entity; + +architecture test of A is +begin +end architecture; + +entity B is +end entity; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture test of B is + function to_vector(signal d: unsigned(4 downto 0)) return std_ulogic_vector is + begin + return std_ulogic_vector(d); + end function; + + signal s: unsigned(4 downto 0) := (others => '0'); +begin + test: entity work.A + port map( + x => to_vector(s) + ); +end architecture; diff --git a/testsuite/gna/issue1123/b1.vhdl b/testsuite/gna/issue1123/b1.vhdl new file mode 100644 index 000000000..479da960f --- /dev/null +++ b/testsuite/gna/issue1123/b1.vhdl @@ -0,0 +1,32 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity A is +port(x: in std_ulogic_vector(4 downto 0)); +end entity; + +architecture test of A is +begin +end architecture; + +entity B is +end entity; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +architecture test of B is + function to_vector(d: unsigned(4 downto 0)) return std_ulogic_vector is + begin + return std_ulogic_vector(d); + end function; + + signal s: unsigned(4 downto 0) := (others => '0'); +begin + test: entity work.A + port map( + x => to_vector(s) + ); +end architecture; diff --git a/testsuite/gna/issue1123/testsuite.sh b/testsuite/gna/issue1123/testsuite.sh new file mode 100755 index 000000000..af42e86fe --- /dev/null +++ b/testsuite/gna/issue1123/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure b.vhdl +analyze b1.vhdl +elab_simulate b + +clean + +echo "Test successful" |