3 files changed, 75 insertions, 0 deletions
diff --git a/testsuite/gna/issue1123/b.vhdl b/testsuite/gna/issue1123/b.vhdl
new file mode 100644
index 000000000..36e18b9e9
--- /dev/null
+++ b/testsuite/gna/issue1123/b.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity A is
+port(x: in std_ulogic_vector(4 downto 0));
+end entity;
+
+architecture test of A is
+begin
+end architecture;
+
+entity B is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture test of B is
+    function to_vector(signal d: unsigned(4 downto 0)) return std_ulogic_vector is
+    begin
+        return std_ulogic_vector(d);
+    end function;
+
+    signal s: unsigned(4 downto 0) := (others => '0');
+begin
+    test: entity work.A
+    port map(
+        x => to_vector(s)
+    );
+end architecture;
diff --git a/testsuite/gna/issue1123/b1.vhdl b/testsuite/gna/issue1123/b1.vhdl
new file mode 100644
index 000000000..479da960f
--- /dev/null
+++ b/testsuite/gna/issue1123/b1.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity A is
+port(x: in std_ulogic_vector(4 downto 0));
+end entity;
+
+architecture test of A is
+begin
+end architecture;
+
+entity B is
+end entity;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+architecture test of B is
+    function to_vector(d: unsigned(4 downto 0)) return std_ulogic_vector is
+    begin
+        return std_ulogic_vector(d);
+    end function;
+
+    signal s: unsigned(4 downto 0) := (others => '0');
+begin
+    test: entity work.A
+    port map(
+        x => to_vector(s)
+    );
+end architecture;
diff --git a/testsuite/gna/issue1123/testsuite.sh b/testsuite/gna/issue1123/testsuite.sh
new file mode 100755
index 000000000..af42e86fe
--- /dev/null
+++ b/testsuite/gna/issue1123/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze_failure b.vhdl
+analyze b1.vhdl
+elab_simulate b
+
+clean
+
+echo "Test successful"