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authorTristan Gingold <tgingold@free.fr>2016-03-15 20:28:56 +0100
committerTristan Gingold <tgingold@free.fr>2016-03-15 20:28:56 +0100
commit37192248646ce7b4688f105877449c640e5039ce (patch)
tree9cc7877a5b50d3e48373a39dcbedd7419c5b35c9 /testsuite/gna/bug040/cmp_977.vhd
parentf4a61202e89d2e29416ae9a4b59bea665336c325 (diff)
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Add bug040 testcase.
Diffstat (limited to 'testsuite/gna/bug040/cmp_977.vhd')
-rw-r--r--testsuite/gna/bug040/cmp_977.vhd26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/bug040/cmp_977.vhd b/testsuite/gna/bug040/cmp_977.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity cmp_977 is
+ port (
+ eq : out std_logic;
+ in1 : in std_logic_vector(31 downto 0);
+ in0 : in std_logic_vector(31 downto 0)
+ );
+end cmp_977;
+
+architecture augh of cmp_977 is
+
+ signal tmp : std_logic;
+
+begin
+
+ -- Compute the result
+ tmp <=
+ '0' when in1 /= in0 else
+ '1';
+
+ -- Set the outputs
+ eq <= tmp;
+
+end architecture;