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author | Tristan Gingold <tgingold@free.fr> | 2015-09-02 18:22:33 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2015-09-02 18:22:33 +0200 |
commit | 40aff7e812f106911b7302cae1fe8fde760639ec (patch) | |
tree | 201f9b84def2795c0b246c9fc3323f2cb4194ae6 /testsuite/gna/bug021/makefile | |
parent | e1a8d8789fcac1d46d381dc2f7803f7c0a0ed970 (diff) | |
download | ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.tar.gz ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.tar.bz2 ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.zip |
Add bug021.
Diffstat (limited to 'testsuite/gna/bug021/makefile')
-rw-r--r-- | testsuite/gna/bug021/makefile | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/gna/bug021/makefile b/testsuite/gna/bug021/makefile new file mode 100644 index 000000000..de9ee8f4b --- /dev/null +++ b/testsuite/gna/bug021/makefile @@ -0,0 +1,43 @@ +
+
+
+all:
+
+
+ rm -rf work
+ mkdir work
+
+
+ ghdl -a --work=work --workdir=work sim_pkg.vhd
+ gcc -c -fPIC sim.c -o sim.o
+
+
+
+ ghdl -a --work=work --workdir=work tb_cosim.vhd
+
+
+ ghdl -e -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork tb_cosim
+
+# ghdl -r tb_lm_cpu
+ ghdl -r tb_cosim --wave=tbencha.ghw --stop-time=100ns
+# ghdl -r tbench --disp-tree=inst --wave=tbench.ghw
+
+# ghdl -r tb_lm_cpu
+
+
+view:
+ gtkwave tbencha.ghw a.sav
+
+
+post:
+ rm -rf work
+ mkdir work
+ ghdl -i ../ise601/netgen/synthesis/MAIS_soc_synthesis.vhd
+ ghdl -i ../rtl/tb_MAIS.vhd
+ ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/*.vhd
+ ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/primitive/*.vhd
+
+
+
+ ghdl -m -g -Punisim -Psimprim --warn-unused --ieee=synopsys -fexplicit tb_lm_cpuvi
+ ghdl -r tb_lm_cpu --disp-tree=inst --wave=tbench.ghw --stop-time=50us
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