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author | Tristan Gingold <tgingold@free.fr> | 2015-09-02 18:22:33 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2015-09-02 18:22:33 +0200 |
commit | 40aff7e812f106911b7302cae1fe8fde760639ec (patch) | |
tree | 201f9b84def2795c0b246c9fc3323f2cb4194ae6 /testsuite/gna/bug021 | |
parent | e1a8d8789fcac1d46d381dc2f7803f7c0a0ed970 (diff) | |
download | ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.tar.gz ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.tar.bz2 ghdl-40aff7e812f106911b7302cae1fe8fde760639ec.zip |
Add bug021.
Diffstat (limited to 'testsuite/gna/bug021')
-rw-r--r-- | testsuite/gna/bug021/makefile | 43 | ||||
-rw-r--r-- | testsuite/gna/bug021/sim.c | 15 | ||||
-rw-r--r-- | testsuite/gna/bug021/sim_pkg.vhd | 35 | ||||
-rw-r--r-- | testsuite/gna/bug021/tb_cosim.vhd | 66 | ||||
-rwxr-xr-x | testsuite/gna/bug021/testsuite.sh | 10 |
5 files changed, 169 insertions, 0 deletions
diff --git a/testsuite/gna/bug021/makefile b/testsuite/gna/bug021/makefile new file mode 100644 index 000000000..de9ee8f4b --- /dev/null +++ b/testsuite/gna/bug021/makefile @@ -0,0 +1,43 @@ +
+
+
+all:
+
+
+ rm -rf work
+ mkdir work
+
+
+ ghdl -a --work=work --workdir=work sim_pkg.vhd
+ gcc -c -fPIC sim.c -o sim.o
+
+
+
+ ghdl -a --work=work --workdir=work tb_cosim.vhd
+
+
+ ghdl -e -Wl,sim.o --ieee=synopsys -fexplicit --workdir=work -Pwork tb_cosim
+
+# ghdl -r tb_lm_cpu
+ ghdl -r tb_cosim --wave=tbencha.ghw --stop-time=100ns
+# ghdl -r tbench --disp-tree=inst --wave=tbench.ghw
+
+# ghdl -r tb_lm_cpu
+
+
+view:
+ gtkwave tbencha.ghw a.sav
+
+
+post:
+ rm -rf work
+ mkdir work
+ ghdl -i ../ise601/netgen/synthesis/MAIS_soc_synthesis.vhd
+ ghdl -i ../rtl/tb_MAIS.vhd
+ ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/*.vhd
+ ghdl -i --work=unisim /opt/Xilinx/14.5/ISE_DS/ISE/vhdl/src/unisims/primitive/*.vhd
+
+
+
+ ghdl -m -g -Punisim -Psimprim --warn-unused --ieee=synopsys -fexplicit tb_lm_cpuvi
+ ghdl -r tb_lm_cpu --disp-tree=inst --wave=tbench.ghw --stop-time=50us
diff --git a/testsuite/gna/bug021/sim.c b/testsuite/gna/bug021/sim.c new file mode 100644 index 000000000..8b12aeb67 --- /dev/null +++ b/testsuite/gna/bug021/sim.c @@ -0,0 +1,15 @@ + +#include <stdio.h> + + +void street(int number) +{ + printf("street: %d\n",number); +} + + +void house(int number) +{ + printf("house: %d\n",number); +} + diff --git a/testsuite/gna/bug021/sim_pkg.vhd b/testsuite/gna/bug021/sim_pkg.vhd new file mode 100644 index 000000000..00df0eeb6 --- /dev/null +++ b/testsuite/gna/bug021/sim_pkg.vhd @@ -0,0 +1,35 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +package sim_pkg is + + + + procedure house ( reg : in integer ); + attribute foreign of house : + procedure is "VHPIDIRECT house"; + + + procedure street ( reg : in integer ); + attribute foreign of street : + procedure is "VHPIDIRECT street"; +end; + + +package body sim_pkg is + + + procedure house (reg : in integer) is + begin + assert false report "VHPI" severity failure; + end house; + + procedure street (reg : in integer) is + begin + assert false report "VHPI" severity failure; + end street; + +end sim_pkg; diff --git a/testsuite/gna/bug021/tb_cosim.vhd b/testsuite/gna/bug021/tb_cosim.vhd new file mode 100644 index 000000000..2139d4471 --- /dev/null +++ b/testsuite/gna/bug021/tb_cosim.vhd @@ -0,0 +1,66 @@ +-------------------------------------------------------------------------------- +-- Company: Dossmatik GmbH +-- Create Date: 21:08:31 05/17/2011 + +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench +-- test for VHPI +-------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.sim_pkg.all; + + +entity tb_cosim is +end tb_cosim; + +architecture behavior of tb_cosim is + + function crc (crc_value : std_logic_vector(31 downto 0) + ) return std_logic_vector is + + variable crc_out : std_logic_vector(31 downto 0); + + begin + crc_out := (crc(3 downto 0)& crc_out(31 downto 4)) xor crc; + return crc_out; + end crc; + + signal random : std_logic_vector ( 31 downto 0):=X"00000000"; + -- Clock period definitions + + constant board_clk_period : time := 20 ns; + + signal board_clk: std_logic; +begin + + + + process (board_clk) + begin + if rising_edge(board_clk) then + street(to_integer(unsigned(random))); + random<=crc(random); + end if; + end process; + + + + + + -- Clock process definitions + board_clk_process : process + begin + board_clk <= '0'; + wait for board_clk_period/2; + board_clk <= '1'; + wait for board_clk_period/2; + end process; + + + end; diff --git a/testsuite/gna/bug021/testsuite.sh b/testsuite/gna/bug021/testsuite.sh new file mode 100755 index 000000000..428744dc3 --- /dev/null +++ b/testsuite/gna/bug021/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze sim_pkg.vhd +analyze_failure tb_cosim.vhd + +clean + +echo "Test successful" |