vhdl-nodes: reorder, add iir_kinds_structural_statement

2 files changed, 36 insertions, 20 deletions

diff --git a/pyGHDL/libghdl/vhdl/nodes.py b/pyGHDL/libghdl/vhdl/nodes.py
index eba36f86c..619d5c2c4 100644
--- a/pyGHDL/libghdl/vhdl/nodes.py
+++ b/pyGHDL/libghdl/vhdl/nodes.py
@@ -618,11 +618,6 @@ class Iir_Kinds:
         Iir_Kind.Procedure_Body,
     ]
 
-    Process_Statement = [
-        Iir_Kind.Sensitized_Process_Statement,
-        Iir_Kind.Process_Statement,
-    ]
-
     Interface_Object_Declaration = [
         Iir_Kind.Interface_Constant_Declaration,
         Iir_Kind.Interface_Variable_Declaration,
@@ -985,6 +980,14 @@ class Iir_Kinds:
         Iir_Kind.Component_Instantiation_Statement,
     ]
 
+    Structural_Statement = [
+        Iir_Kind.Block_Statement,
+        Iir_Kind.If_Generate_Statement,
+        Iir_Kind.Case_Generate_Statement,
+        Iir_Kind.For_Generate_Statement,
+        Iir_Kind.Component_Instantiation_Statement,
+    ]
+
     Simple_Concurrent_Statement = [
         Iir_Kind.Sensitized_Process_Statement,
         Iir_Kind.Process_Statement,
@@ -1000,6 +1003,17 @@ class Iir_Kinds:
         Iir_Kind.Psl_Restrict_Directive,
     ]
 
+    Process_Statement = [
+        Iir_Kind.Sensitized_Process_Statement,
+        Iir_Kind.Process_Statement,
+    ]
+
+    Concurrent_Signal_Assignment = [
+        Iir_Kind.Concurrent_Simple_Signal_Assignment,
+        Iir_Kind.Concurrent_Conditional_Signal_Assignment,
+        Iir_Kind.Concurrent_Selected_Signal_Assignment,
+    ]
+
     Psl_Property_Directive = [
         Iir_Kind.Psl_Assert_Directive,
         Iir_Kind.Psl_Assume_Directive,
@@ -1023,12 +1037,6 @@ class Iir_Kinds:
         Iir_Kind.For_Generate_Statement,
     ]
 
-    Concurrent_Signal_Assignment = [
-        Iir_Kind.Concurrent_Simple_Signal_Assignment,
-        Iir_Kind.Concurrent_Conditional_Signal_Assignment,
-        Iir_Kind.Concurrent_Selected_Signal_Assignment,
-    ]
-
     If_Case_Generate_Statement = [
         Iir_Kind.If_Generate_Statement,
         Iir_Kind.Case_Generate_Statement,
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index cc9279d1b..1e97286d0 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -6594,10 +6594,6 @@ package Vhdl.Nodes is
      Iir_Kind_Function_Body ..
      Iir_Kind_Procedure_Body;
 
-   subtype Iir_Kinds_Process_Statement is Iir_Kind range
-     Iir_Kind_Sensitized_Process_Statement ..
-     Iir_Kind_Process_Statement;
-
    subtype Iir_Kinds_Interface_Object_Declaration is Iir_Kind range
      Iir_Kind_Interface_Constant_Declaration ..
    --Iir_Kind_Interface_Variable_Declaration
@@ -6891,6 +6887,14 @@ package Vhdl.Nodes is
    --Iir_Kind_For_Generate_Statement
      Iir_Kind_Component_Instantiation_Statement;
 
+   --  Nice classification from AMS vhdl.
+   subtype Iir_Kinds_Structural_Statement is Iir_Kind range
+     Iir_Kind_Block_Statement ..
+   --Iir_Kind_If_Generate_Statement
+   --Iir_Kind_Case_Generate_Statement
+   --Iir_Kind_For_Generate_Statement
+     Iir_Kind_Component_Instantiation_Statement;
+
    subtype Iir_Kinds_Simple_Concurrent_Statement is Iir_Kind range
      Iir_Kind_Sensitized_Process_Statement ..
    --Iir_Kind_Process_Statement
@@ -6905,6 +6909,15 @@ package Vhdl.Nodes is
    --Iir_Kind_Psl_Cover_Directive
      Iir_Kind_Psl_Restrict_Directive;
 
+   subtype Iir_Kinds_Process_Statement is Iir_Kind range
+     Iir_Kind_Sensitized_Process_Statement ..
+     Iir_Kind_Process_Statement;
+
+   subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range
+     Iir_Kind_Concurrent_Simple_Signal_Assignment ..
+   --Iir_Kind_Concurrent_Conditional_Signal_Assignment
+     Iir_Kind_Concurrent_Selected_Signal_Assignment;
+
    subtype Iir_Kinds_Psl_Property_Directive is Iir_Kind range
      Iir_Kind_Psl_Assert_Directive ..
      Iir_Kind_Psl_Assume_Directive;
@@ -6924,11 +6937,6 @@ package Vhdl.Nodes is
    --Iir_Kind_Case_Generate_Statement
      Iir_Kind_For_Generate_Statement;
 
-   subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range
-     Iir_Kind_Concurrent_Simple_Signal_Assignment ..
-   --Iir_Kind_Concurrent_Conditional_Signal_Assignment
-     Iir_Kind_Concurrent_Selected_Signal_Assignment;
-
    subtype Iir_Kinds_If_Case_Generate_Statement is Iir_Kind range
      Iir_Kind_If_Generate_Statement ..
      Iir_Kind_Case_Generate_Statement;