diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 37 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 5 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 2 |
4 files changed, 31 insertions, 20 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 700846bbb..43ca5fee3 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1199,24 +1199,25 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320 Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321 Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322 - Ieee_Std_Logic_Signed_Add_Slv_Slv = 323 - Ieee_Std_Logic_Signed_Add_Slv_Int = 324 - Ieee_Std_Logic_Signed_Add_Int_Slv = 325 - Ieee_Std_Logic_Signed_Add_Slv_Sl = 326 - Ieee_Std_Logic_Signed_Add_Sl_Slv = 327 - Ieee_Std_Logic_Signed_Sub_Slv_Slv = 328 - Ieee_Std_Logic_Signed_Sub_Slv_Int = 329 - Ieee_Std_Logic_Signed_Sub_Int_Slv = 330 - Ieee_Std_Logic_Signed_Sub_Slv_Sl = 331 - Ieee_Std_Logic_Signed_Sub_Sl_Slv = 332 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 333 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 334 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 335 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 336 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 337 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 338 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 339 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 340 + Ieee_Std_Logic_Unsigned_Conv_Integer = 323 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 324 + Ieee_Std_Logic_Signed_Add_Slv_Int = 325 + Ieee_Std_Logic_Signed_Add_Int_Slv = 326 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 327 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 328 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 329 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 330 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 331 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 332 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 333 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 334 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 335 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 336 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 337 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 338 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 339 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 340 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 341 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index d6574667b..8f85a8817 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -513,7 +513,9 @@ package body Synth.Oper is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int => -- "-" (Unsigned, Natural) return Synth_Dyadic_Uns_Nat (Id_Sub); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Sub, True); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int @@ -1078,7 +1080,8 @@ package body Synth.Oper is end if; end; when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => -- UNSIGNED to Natural. declare Int_Type : constant Type_Acc := diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 9e2bb5269..c3b30be8e 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -184,6 +184,11 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is else -- Monadic function. case Get_Identifier (Decl) is + when Name_Conv_Integer => + if Sign = Pkg_Unsigned then + Res := + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer; + end if; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index bd25fb805..8de95478b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5093,6 +5093,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer, + -- Std_Logic_Signed (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, |