vhdl: recognize ieee.numeric_std_unsigned. For #1572

6 files changed, 162 insertions, 25 deletions

diff --git a/src/std_names.adb b/src/std_names.adb
index 0545fdbaa..e98df740a 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -615,17 +615,18 @@ package body Std_Names is
       Def ("built_in",              Name_Built_In);
       Def ("none",                  Name_None);
 
-      Def ("ieee",               Name_Ieee);
-      Def ("std_logic_1164",     Name_Std_Logic_1164);
-      Def ("vital_timing",       Name_VITAL_Timing);
-      Def ("numeric_std",        Name_Numeric_Std);
-      Def ("numeric_bit",        Name_Numeric_Bit);
-      Def ("std_logic_arith",    Name_Std_Logic_Arith);
-      Def ("std_logic_signed",   Name_Std_Logic_Signed);
-      Def ("std_logic_unsigned", Name_Std_Logic_Unsigned);
-      Def ("std_logic_textio",   Name_Std_Logic_Textio);
-      Def ("std_logic_misc",     Name_Std_Logic_Misc);
-      Def ("math_real",          Name_Math_Real);
+      Def ("ieee",                  Name_Ieee);
+      Def ("std_logic_1164",        Name_Std_Logic_1164);
+      Def ("vital_timing",          Name_VITAL_Timing);
+      Def ("numeric_std",           Name_Numeric_Std);
+      Def ("numeric_bit",           Name_Numeric_Bit);
+      Def ("numeric_std_unsigned",  Name_Numeric_Std_Unsigned);
+      Def ("std_logic_arith",       Name_Std_Logic_Arith);
+      Def ("std_logic_signed",      Name_Std_Logic_Signed);
+      Def ("std_logic_unsigned",    Name_Std_Logic_Unsigned);
+      Def ("std_logic_textio",      Name_Std_Logic_Textio);
+      Def ("std_logic_misc",        Name_Std_Logic_Misc);
+      Def ("math_real",             Name_Math_Real);
 
       Def ("std_ulogic",         Name_Std_Ulogic);
       Def ("std_ulogic_vector",  Name_Std_Ulogic_Vector);
diff --git a/src/std_names.ads b/src/std_names.ads
index 0d8950171..90ad19fe6 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -695,19 +695,20 @@ package Std_Names is
    Name_None :                  constant Name_Id := Name_First_Misc + 041;
    Name_Last_Misc :             constant Name_Id := Name_None;
 
-   Name_First_Ieee_Pkg     : constant Name_Id := Name_Last_Misc + 1;
-   Name_Ieee               : constant Name_Id := Name_First_Ieee_Pkg + 000;
-   Name_Std_Logic_1164     : constant Name_Id := Name_First_Ieee_Pkg + 001;
-   Name_VITAL_Timing       : constant Name_Id := Name_First_Ieee_Pkg + 002;
-   Name_Numeric_Std        : constant Name_Id := Name_First_Ieee_Pkg + 003;
-   Name_Numeric_Bit        : constant Name_Id := Name_First_Ieee_Pkg + 004;
-   Name_Std_Logic_Arith    : constant Name_Id := Name_First_Ieee_Pkg + 005;
-   Name_Std_Logic_Signed   : constant Name_Id := Name_First_Ieee_Pkg + 006;
-   Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee_Pkg + 007;
-   Name_Std_Logic_Textio   : constant Name_Id := Name_First_Ieee_Pkg + 008;
-   Name_Std_Logic_Misc     : constant Name_Id := Name_First_Ieee_Pkg + 009;
-   Name_Math_Real          : constant Name_Id := Name_First_Ieee_Pkg + 010;
-   Name_Last_Ieee_Pkg      : constant Name_Id := Name_Math_Real;
+   Name_First_Ieee_Pkg       : constant Name_Id := Name_Last_Misc + 1;
+   Name_Ieee                 : constant Name_Id := Name_First_Ieee_Pkg + 000;
+   Name_Std_Logic_1164       : constant Name_Id := Name_First_Ieee_Pkg + 001;
+   Name_VITAL_Timing         : constant Name_Id := Name_First_Ieee_Pkg + 002;
+   Name_Numeric_Std          : constant Name_Id := Name_First_Ieee_Pkg + 003;
+   Name_Numeric_Bit          : constant Name_Id := Name_First_Ieee_Pkg + 004;
+   Name_Numeric_Std_Unsigned : constant Name_Id := Name_First_Ieee_Pkg + 005;
+   Name_Std_Logic_Arith      : constant Name_Id := Name_First_Ieee_Pkg + 006;
+   Name_Std_Logic_Signed     : constant Name_Id := Name_First_Ieee_Pkg + 007;
+   Name_Std_Logic_Unsigned   : constant Name_Id := Name_First_Ieee_Pkg + 008;
+   Name_Std_Logic_Textio     : constant Name_Id := Name_First_Ieee_Pkg + 009;
+   Name_Std_Logic_Misc       : constant Name_Id := Name_First_Ieee_Pkg + 010;
+   Name_Math_Real            : constant Name_Id := Name_First_Ieee_Pkg + 011;
+   Name_Last_Ieee_Pkg        : constant Name_Id := Name_Math_Real;
 
    Name_First_Ieee_Name    : constant Name_Id := Name_Last_Ieee_Pkg + 1;
    Name_Std_Ulogic         : constant Name_Id := Name_First_Ieee_Name + 000;
diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb
new file mode 100644
index 000000000..16450f5a6
--- /dev/null
+++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb
@@ -0,0 +1,105 @@
+--  Nodes recognizer for ieee.std_logic_unsigned and ieee.std_logic_signed
+--  Copyright (C) 2021 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+with Vhdl.Std_Package;
+with Std_Names; use Std_Names;
+with Vhdl.Ieee.Std_Logic_1164;
+with Vhdl.Errors;
+
+package body Vhdl.Ieee.Numeric_Std_Unsigned is
+   type Arg_Kind is (Arg_Slv, Arg_Int, Arg_Log);
+
+   Error : exception;
+
+   procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind)
+   is
+      Arg_Type : constant Iir := Get_Type (Arg);
+   begin
+      if Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition
+        or else Arg_Type = Vhdl.Std_Package.Natural_Subtype_Definition
+      then
+         Kind := Arg_Int;
+      elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type
+        or else Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Type
+      then
+         Kind := Arg_Log;
+      elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type
+        or else Arg_Type = Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type
+      then
+         Kind := Arg_Slv;
+      else
+         raise Error;
+      end if;
+   end Classify_Arg;
+
+   procedure Extract_Declaration (Decl : Iir)
+   is
+      Arg1, Arg2 : Iir;
+      Arg1_Kind  : Arg_Kind;
+      Res : Iir_Predefined_Functions;
+   begin
+      Arg1 := Get_Interface_Declaration_Chain (Decl);
+      if Is_Null (Arg1) then
+         raise Error;
+      end if;
+
+      Res := Iir_Predefined_None;
+
+      Classify_Arg (Arg1, Arg1_Kind);
+      Arg2 := Get_Chain (Arg1);
+      if Is_Valid (Arg2) then
+         --  Dyadic function.
+         null;
+      else
+         --  Monadic function.
+         case Get_Identifier (Decl) is
+            when Name_To_Integer =>
+               pragma Assert (Arg1_Kind = Arg_Slv);
+               Res :=
+                 Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Integer_Slv_Nat;
+            when others =>
+               null;
+         end case;
+      end if;
+      Set_Implicit_Definition (Decl, Res);
+   end Extract_Declaration;
+
+   procedure Extract_Declarations (Pkg : Iir_Package_Declaration)
+   is
+      Decl : Iir;
+   begin
+      Decl := Get_Declaration_Chain (Pkg);
+
+      Decl := Skip_Copyright_Notice (Decl);
+
+      --  Handle functions.
+      while Is_Valid (Decl) loop
+         case Get_Kind (Decl) is
+            when Iir_Kind_Function_Declaration =>
+               Extract_Declaration (Decl);
+            when Iir_Kind_Non_Object_Alias_Declaration =>
+               null;
+            when others =>
+               Vhdl.Errors.Error_Kind ("extract_declarations", Decl);
+               raise Error;
+         end case;
+
+         Decl := Get_Chain (Decl);
+      end loop;
+   end Extract_Declarations;
+end Vhdl.Ieee.Numeric_Std_Unsigned;
diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.ads b/src/vhdl/vhdl-ieee-numeric_std_unsigned.ads
new file mode 100644
index 000000000..f90eb5c7a
--- /dev/null
+++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.ads
@@ -0,0 +1,22 @@
+--  Nodes recognizer for ieee.std_logic_unsigned and ieee.std_logic_signed.
+--  Copyright (C) 2021 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+package Vhdl.Ieee.Numeric_Std_Unsigned is
+   --  Extract declarations from PKG .
+   procedure Extract_Declarations (Pkg : Iir_Package_Declaration);
+end Vhdl.Ieee.Numeric_Std_Unsigned;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 855dccebd..f092fd598 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5873,6 +5873,9 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_To_01_Uns,
       Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn,
 
+      --  Numeric_Std_Unsigned (ieee2008)
+      Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Integer_Slv_Nat,
+
       --  Math_Real
       Iir_Predefined_Ieee_Math_Real_Ceil,
       Iir_Predefined_Ieee_Math_Real_Floor,
diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb
index 5477a3136..c21c1b3d1 100644
--- a/src/vhdl/vhdl-post_sems.adb
+++ b/src/vhdl/vhdl-post_sems.adb
@@ -21,6 +21,7 @@ with Vhdl.Sem_Specs;
 with Vhdl.Ieee.Std_Logic_1164;
 with Vhdl.Ieee.Vital_Timing;
 with Vhdl.Ieee.Numeric;
+with Vhdl.Ieee.Numeric_Std_Unsigned;
 with Vhdl.Ieee.Math_Real;
 with Vhdl.Ieee.Std_Logic_Unsigned;
 with Vhdl.Ieee.Std_Logic_Arith;
@@ -60,7 +61,11 @@ package body Vhdl.Post_Sems is
                when Name_VITAL_Timing =>
                   Vhdl.Ieee.Vital_Timing.Extract_Declarations (Lib_Unit);
                when Name_Numeric_Std =>
-                  Vhdl.Ieee.Numeric.Extract_Std_Declarations (Lib_Unit);
+                  Vhdl.Ieee.Numeric.Extract_Std_Declarations
+                    (Lib_Unit);
+               when Name_Numeric_Std_Unsigned =>
+                  Vhdl.Ieee.Numeric_Std_Unsigned.Extract_Declarations
+                    (Lib_Unit);
                when Name_Math_Real =>
                   Vhdl.Ieee.Math_Real.Extract_Declarations (Lib_Unit);
                when Name_Std_Logic_Unsigned =>