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| author | Tristan Gingold <tgingold@free.fr> | 2023-04-14 16:46:45 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-04-14 16:46:45 +0200 |
| commit | 6526eae3f265fc490adeeb537eb938b68a4b02d9 (patch) | |
| tree | 8ded0648805fb4134ac2dd57e79f96cd211eec66 /src | |
| parent | de71ceb21895464e2e716cf84351f100644f49b0 (diff) | |
| download | ghdl-6526eae3f265fc490adeeb537eb938b68a4b02d9.tar.gz ghdl-6526eae3f265fc490adeeb537eb938b68a4b02d9.tar.bz2 ghdl-6526eae3f265fc490adeeb537eb938b68a4b02d9.zip | |
vhdl: recognize conv_signed. For #2408
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 5 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 0786f753e..b3f6e9c81 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -50,6 +50,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log); + Conv_Sgn_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Log); + Conv_Int_Patterns : constant Conv_Pattern_Type := (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, @@ -521,6 +527,8 @@ package body Vhdl.Ieee.Std_Logic_Arith is Def := Handle_Bin (Mul_Patterns); when Name_Conv_Unsigned => Def := Handle_Conv (Conv_Uns_Patterns); + when Name_Conv_Signed => + Def := Handle_Conv (Conv_Sgn_Patterns); when Name_Conv_Std_Logic_Vector => Def := Handle_Conv (Conv_Vec_Patterns); when Name_Op_Less => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 3d9561662..95676af3e 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6289,6 +6289,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Log, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, |