From 1ee18afbe800ede060e8e0daca47b188137ee4eb Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 10 Oct 2019 18:40:17 +0200 Subject: netlists-disp_vhdl: fix pasto on id_asr. --- src/synth/netlists-disp_vhdl.adb | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 05e94c205..880bfb0db 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -770,10 +770,14 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= std_logic_vector " & "(shift_left (\ui0, to_integer (\ui1)));" & NL, Inst); + when Id_Lsr => + Disp_Template + (" \o0 <= std_logic_vector " + & "(shift_right (\ui0, to_integer(\ui1)));" & NL, Inst); when Id_Asr => Disp_Template (" \o0 <= std_logic_vector " - & "(shift_left (\si0, to_integer (\ui1)));" & NL, Inst); + & "(shift_right (\si0, to_integer (\ui1)));" & NL, Inst); when Id_Rol => Disp_Template (" \o0 <= std_logic_vector " @@ -881,10 +885,6 @@ package body Netlists.Disp_Vhdl is Inst, (0 => Ow)); end if; end; - when Id_Lsr => - Disp_Template - (" \o0 <= std_logic_vector " - & "(shift_right (\ui0, to_integer(\ui1)));" & NL, Inst); when Id_Red_Or => declare Iw : constant Width := Get_Width (Get_Input_Net (Inst, 0)); -- cgit v1.2.3