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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-30 14:43:33 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-30 14:43:33 +0200 |
| commit | fdad6f32d73f5207b999e7cebe8f1c25d33ade09 (patch) | |
| tree | 38946180f57122575055f90d5e9249ee445979d2 /src/vhdl | |
| parent | c9a1948c12ec5262db925811d32e6a5886172abc (diff) | |
| download | ghdl-fdad6f32d73f5207b999e7cebe8f1c25d33ade09.tar.gz ghdl-fdad6f32d73f5207b999e7cebe8f1c25d33ade09.tar.bz2 ghdl-fdad6f32d73f5207b999e7cebe8f1c25d33ade09.zip | |
vhdl: recognize more predefined std_logic_unsigned functions.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 16 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 |
2 files changed, 24 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 9fbdac603..5acf9ae4f 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -33,6 +33,18 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv, others => Iir_Predefined_None); + Lt_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, + others => Iir_Predefined_None); + + Le_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, + others => Iir_Predefined_None); + Add_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, @@ -114,6 +126,10 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Less => + Handle_Binary (Lt_Patterns); + when Name_Op_Less_Equal => + Handle_Binary (Le_Patterns); when Name_Op_Plus => Handle_Binary (Add_Patterns); when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 2e9e8c049..ec354499d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4886,6 +4886,14 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv |