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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-07-16 18:40:53 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-07-16 18:40:53 +0200 |
| commit | db958a4299a5b22c6ed6a7ae634e0bbe534708ac (patch) | |
| tree | 301866ca2c7e1af61f12a26c79f624e8975b67a1 /src/vhdl | |
| parent | 32933b13ec02e0ea60504d9c2c354c198e8e5c13 (diff) | |
| download | ghdl-db958a4299a5b22c6ed6a7ae634e0bbe534708ac.tar.gz ghdl-db958a4299a5b22c6ed6a7ae634e0bbe534708ac.tar.bz2 ghdl-db958a4299a5b22c6ed6a7ae634e0bbe534708ac.zip | |
synth: add > and >= operators (#870)
* synth: add > and >= operators
* synth: update ghdlsynth_gates.h
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 60 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 |
2 files changed, 68 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 24958e08a..9f57e7787 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -127,6 +127,60 @@ package body Vhdl.Ieee.Numeric is (others => (others => Iir_Predefined_None))); + Le_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Le_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Le_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Le_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Le_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Le_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + + Gt_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Gt_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Gt_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Gt_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Gt_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + + Ge_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Ge_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Ge_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + Neg_Patterns : constant Unary_Pattern_Type := (Pkg_Std => (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Neg_Uns, @@ -345,6 +399,12 @@ package body Vhdl.Ieee.Numeric is Handle_Binary (Ne_Patterns); when Name_Op_Less => Handle_Binary (Lt_Patterns); + when Name_Op_Less_Equal => + Handle_Binary (Le_Patterns); + when Name_Op_Greater => + Handle_Binary (Gt_Patterns); + when Name_Op_Greater_Equal => + Handle_Binary (Ge_Patterns); when Name_To_Bstring | Name_To_Ostring | Name_To_Hstring => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 5a71204b7..c6f4a9c2a 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4965,6 +4965,14 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Gt_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Int_Slv |