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authorTristan Gingold <tgingold@free.fr>2023-02-08 16:07:23 +0100
committerTristan Gingold <tgingold@free.fr>2023-02-08 16:07:23 +0100
commitd0129fb0e2e89128de8d8569a32cd8fb97fa0b8c (patch)
tree3b70d49bd78c8b979c46a41be30fb241bfaf418a /src/vhdl
parentf575f7cf61f96be6201a5308d1747ca57c920185 (diff)
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trans-chap8: fix a crash while checking bounds in signal assignments.
Fix #2346
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/translate/trans-chap8.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb
index 42d8473e1..b5393479e 100644
--- a/src/vhdl/translate/trans-chap8.adb
+++ b/src/vhdl/translate/trans-chap8.adb
@@ -4591,7 +4591,7 @@ package body Trans.Chap8 is
begin
if Get_Kind (Target) = Iir_Kind_Aggregate then
-- The target is an aggregate.
- Chap3.Translate_Anonymous_Subtype_Definition (Target_Type, False);
+ Chap3.Translate_Anonymous_Subtype_Definition (Target_Type, True);
Target_Tinfo := Get_Info (Target_Type);
Targ := Create_Temp (Target_Tinfo, Mode_Signal);
if Target_Tinfo.Type_Mode in Type_Mode_Unbounded then