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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-06 07:25:26 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-06 07:25:26 +0200 |
| commit | c0b6dbfcc55da8cde4ad00782f0b27cd3abba6e6 (patch) | |
| tree | 480d55829ead0ec83c54d179672ea18bb314c077 /src/vhdl | |
| parent | 60b3a419cfbd279ff4c477cfcab924b646d5c444 (diff) | |
| download | ghdl-c0b6dbfcc55da8cde4ad00782f0b27cd3abba6e6.tar.gz ghdl-c0b6dbfcc55da8cde4ad00782f0b27cd3abba6e6.tar.bz2 ghdl-c0b6dbfcc55da8cde4ad00782f0b27cd3abba6e6.zip | |
synth-vhdl_eval: recognize and handle to_stdulogicvector
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric_std_unsigned.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb index f8c87408b..06baad51d 100644 --- a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb +++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb @@ -77,6 +77,12 @@ package body Vhdl.Ieee.Numeric_Std_Unsigned is elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv; end if; + when Name_To_Stdulogicvector => + if Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv; + end if; when Name_Resize => if Arg2_Kind = Arg_Int then Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c0d344dda..970063e64 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6034,6 +6034,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat, Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat, Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv, @@ -6041,10 +6044,14 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv, -- Math_Real + Iir_Predefined_Ieee_Math_Real_Sign, Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Floor, Iir_Predefined_Ieee_Math_Real_Round, + Iir_Predefined_Ieee_Math_Real_Trunc, + Iir_Predefined_Ieee_Math_Real_Log, Iir_Predefined_Ieee_Math_Real_Log2, + Iir_Predefined_Ieee_Math_Real_Log10, Iir_Predefined_Ieee_Math_Real_Sin, Iir_Predefined_Ieee_Math_Real_Cos, Iir_Predefined_Ieee_Math_Real_Arctan, |