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author | Tristan Gingold <tgingold@free.fr> | 2019-07-20 11:52:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-20 12:22:44 +0200 |
commit | be154c721dd26287173a654bec74cf6a2fc99596 (patch) | |
tree | 9d84292d1a4bfc28a69caa9b08b207e1c10466ca /src/vhdl | |
parent | a4dc62f6b5a8886085cf9364a66f3a118ff020e3 (diff) | |
download | ghdl-be154c721dd26287173a654bec74cf6a2fc99596.tar.gz ghdl-be154c721dd26287173a654bec74cf6a2fc99596.tar.bz2 ghdl-be154c721dd26287173a654bec74cf6a2fc99596.zip |
synth: initial support for for-generate statement.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/vhdl-annotations.adb | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 077c66e99..f45827edb 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -942,7 +942,7 @@ package body Vhdl.Annotations is Block_Info.Nbr_Instances := Block_Info.Nbr_Instances + 1; if It /= Null_Iir then - Annotate_Declaration (Info, It); + Create_Object_Info (Info, It); end if; Annotate_Declaration_List (Info, Get_Declaration_Chain (Bod)); Annotate_Concurrent_Statements_List @@ -963,12 +963,15 @@ package body Vhdl.Annotations is end Annotate_If_Generate_Statement; procedure Annotate_For_Generate_Statement - (Block_Info : Sim_Info_Acc; Stmt : Iir) is + (Block_Info : Sim_Info_Acc; Stmt : Iir) + is + Param : constant Iir := Get_Parameter_Specification (Stmt); begin + -- Elaborate the subtype in the current block. + Annotate_Declaration_Type (Block_Info, Param); + Annotate_Generate_Statement_Body - (Block_Info, - Get_Generate_Statement_Body (Stmt), - Get_Parameter_Specification (Stmt)); + (Block_Info, Get_Generate_Statement_Body (Stmt), Param); end Annotate_For_Generate_Statement; procedure Annotate_Case_Generate_Statement |