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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-10 06:36:49 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-11 15:02:48 +0200 |
| commit | bb357cf03c7e956db1539712fd64353b6d87872d (patch) | |
| tree | 4a78aaec7fad9a0e9400270cf337a75b31832920 /src/vhdl | |
| parent | afeb3e1a54881dd3ae0a1bd4e01f1ef46f9ef0f6 (diff) | |
| download | ghdl-bb357cf03c7e956db1539712fd64353b6d87872d.tar.gz ghdl-bb357cf03c7e956db1539712fd64353b6d87872d.tar.bz2 ghdl-bb357cf03c7e956db1539712fd64353b6d87872d.zip | |
vhdl: recognize ieee.math_real.sign, fix is_x recogn.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-math_real.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 20 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 4 |
3 files changed, 20 insertions, 6 deletions
diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index 1881bb322..d52b8ae85 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -40,6 +40,8 @@ package body Vhdl.Ieee.Math_Real is when Iir_Kind_Function_Declaration => Def := Iir_Predefined_None; case Get_Identifier (Decl) is + when Name_Sign => + Def := Iir_Predefined_Ieee_Math_Real_Sign; when Name_Mod => Def := Iir_Predefined_Ieee_Math_Real_Mod; when Name_Ceil => diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index ff2d95190..207d2f0c5 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -383,6 +383,20 @@ package body Vhdl.Ieee.Std_Logic_1164 is elsif Is_Scalar_Function (Decl) then Predefined := Iir_Predefined_Ieee_1164_To_X01_Log; end if; + when Name_To_UX01 => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Log; + end if; + when Name_To_X01Z => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Log; + end if; when Name_To_Hstring => Predefined := Iir_Predefined_Ieee_1164_To_Hstring; when Name_To_Ostring => @@ -413,8 +427,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_Condition_Operator; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Log; when others => Predefined := Iir_Predefined_None; end case; @@ -452,8 +465,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Xnor => Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Slv; when others => Predefined := Iir_Predefined_None; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index f9b29cf78..c1868bfc7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5669,8 +5669,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_UX01_Bv_Suv, Iir_Predefined_Ieee_1164_To_UX01_Bit_Log, - Iir_Predefined_Ieee_1164_Vector_Is_X, - Iir_Predefined_Ieee_1164_Scalar_Is_X, + Iir_Predefined_Ieee_1164_Is_X_Slv, + Iir_Predefined_Ieee_1164_Is_X_Log, Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, |