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author | Tristan Gingold <tgingold@free.fr> | 2018-12-14 19:14:03 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2018-12-14 19:14:03 +0100 |
commit | 9ef4ebe51b7290e363cedaf0c2cbf72ccef2443f (patch) | |
tree | b08899b53f097a770bb0ee8a06fbff23ebef0f52 /src/vhdl | |
parent | d679149045aaf9eab462b98f67d4064791e2ff40 (diff) | |
download | ghdl-9ef4ebe51b7290e363cedaf0c2cbf72ccef2443f.tar.gz ghdl-9ef4ebe51b7290e363cedaf0c2cbf72ccef2443f.tar.bz2 ghdl-9ef4ebe51b7290e363cedaf0c2cbf72ccef2443f.zip |
files_map: renaming for consistency.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/errorout.adb | 2 | ||||
-rw-r--r-- | src/vhdl/python/libghdl/thin.py | 6 | ||||
-rw-r--r-- | src/vhdl/simulate/simul-debugger.adb | 4 | ||||
-rw-r--r-- | src/vhdl/std_package.adb | 2 |
4 files changed, 10 insertions, 4 deletions
diff --git a/src/vhdl/errorout.adb b/src/vhdl/errorout.adb index cdeb28ee4..be02cea1c 100644 --- a/src/vhdl/errorout.adb +++ b/src/vhdl/errorout.adb @@ -62,7 +62,7 @@ package body Errorout is is Line_Pos : Source_Ptr; begin - Line_Pos := Line_To_Position (E.File, E.Line); + Line_Pos := File_Line_To_Position (E.File, E.Line); return Coord_To_Col (E.File, Line_Pos, E.Offset); end Get_Error_Col; diff --git a/src/vhdl/python/libghdl/thin.py b/src/vhdl/python/libghdl/thin.py index 4de91833d..19a823e7e 100644 --- a/src/vhdl/python/libghdl/thin.py +++ b/src/vhdl/python/libghdl/thin.py @@ -92,6 +92,12 @@ Location_File_Line_To_Offset = libghdl.files_map__location_file_line_to_offset Location_File_Line_To_Col = libghdl.files_map__location_file_line_to_col +File_To_Location = libghdl.files_map__file_to_location + +File_Pos_To_Location = libghdl.files_map__file_pos_to_location + +File_Line_To_Position = libghdl.files_map__file_line_to_position + Get_File_Name = libghdl.files_map__get_file_name Get_File_Buffer = libghdl.files_map__get_file_buffer diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 4ddf1130c..6747179e8 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -1061,7 +1061,7 @@ package body Simul.Debugger is Line := 1; end if; - Pos := Line_To_Position (List_Current_File, Line); + Pos := File_Line_To_Position (List_Current_File, Line); Buf := Get_File_Source (List_Current_File); while Line < List_Current_Line + Radius loop @@ -1121,7 +1121,7 @@ package body Simul.Debugger is begin Location_To_Coord (Loc, File, Line_Pos, Line, Offset); Buf := Get_File_Source (File); - Next_Line_Pos := Line_To_Position (File, Line + 1); + Next_Line_Pos := File_Line_To_Position (File, Line + 1); Put (String (Buf (Line_Pos .. Next_Line_Pos - 1))); end Disp_Source_Line; diff --git a/src/vhdl/std_package.adb b/src/vhdl/std_package.adb index 02f604936..ee6b8cdac 100644 --- a/src/vhdl/std_package.adb +++ b/src/vhdl/std_package.adb @@ -82,7 +82,7 @@ package body Std_Package is end Create_Known_Iir; begin Std_Filename := Name_Table.Get_Identifier ("*std_standard*"); - Std_Location := Files_Map.Source_File_To_Location + Std_Location := Files_Map.File_To_Location (Files_Map.Create_Virtual_Source_File (Std_Filename)); if Create_Iir_Error /= Error_Mark then |