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| author | Tristan Gingold <tgingold@free.fr> | 2017-11-11 09:43:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-11-11 09:43:30 +0100 |
| commit | 8e1372ff23dc77e94bd4c7b52544a4873fab261b (patch) | |
| tree | 107a9938be105ecfab44827cf9de11989b008d5a /src/vhdl | |
| parent | f589c5c13fb533aa3c29453a2916d1da6fec8e11 (diff) | |
| download | ghdl-8e1372ff23dc77e94bd4c7b52544a4873fab261b.tar.gz ghdl-8e1372ff23dc77e94bd4c7b52544a4873fab261b.tar.bz2 ghdl-8e1372ff23dc77e94bd4c7b52544a4873fab261b.zip | |
Rewrite list implementation
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/disp_vhdl.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/iirs.ads | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/vhdl/disp_vhdl.adb b/src/vhdl/disp_vhdl.adb index 744e1f9a2..c35dcfd50 100644 --- a/src/vhdl/disp_vhdl.adb +++ b/src/vhdl/disp_vhdl.adb @@ -794,6 +794,7 @@ package body Disp_Vhdl is is El : Iir; It : List_Iterator; + Is_First : Boolean; begin case List is when Null_Iir_List => @@ -802,10 +803,13 @@ package body Disp_Vhdl is Put ("all"); when others => It := List_Iterate (List); + Is_First := True; while Is_Valid (It) loop El := Get_Element (It); - if not Is_First (It) then + if not Is_First then Put (", "); + else + Is_First := False; end if; Disp_Expression (El); Next (It); diff --git a/src/vhdl/iirs.ads b/src/vhdl/iirs.ads index 4d18f3f88..6b5de4661 100644 --- a/src/vhdl/iirs.ads +++ b/src/vhdl/iirs.ads @@ -5396,8 +5396,6 @@ package Iirs is renames Lists.Iterate_Safe; function Is_Valid (It : List_Iterator) return Boolean renames Lists.Is_Valid; - function Is_First (It : List_Iterator) return Boolean - renames Lists.Is_First; procedure Next (It : in out List_Iterator) renames Lists.Next; function Get_Element (It : List_Iterator) return Iir |