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author | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:20:30 +0200 |
commit | 688173587e76ee89b67b0c0aeb93385c0db08b22 (patch) | |
tree | 5d9fda9535196719ac8a71f90d1a2d62529d42f0 /src/vhdl | |
parent | 17ab141656d8a0ba80309ca4d85e65a038c873e0 (diff) | |
download | ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.gz ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.tar.bz2 ghdl-688173587e76ee89b67b0c0aeb93385c0db08b22.zip |
vhdl: rename Cover_Statement to Cover_Directive.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 2 | ||||
-rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 6 | ||||
-rw-r--r-- | src/vhdl/translate/trans-chap9.adb | 16 | ||||
-rw-r--r-- | src/vhdl/translate/trans-rtis.adb | 8 | ||||
-rw-r--r-- | src/vhdl/vhdl-annotations.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-canon.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-elocations.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-elocations.ads | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-errors.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 10 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes_meta.adb | 36 | ||||
-rw-r--r-- | src/vhdl/vhdl-parse.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-prints.adb | 12 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_psl.adb | 4 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_psl.ads | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-sem_stmts.adb | 4 |
17 files changed, 57 insertions, 57 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index d1c62a2a5..fe89d48c7 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1898,7 +1898,7 @@ package body Simul.Elaboration is | Iir_Kind_Psl_Declaration => null; - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Endpoint_Declaration => Elaborate_Psl_Directive (Instance, Stmt); diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 461aeaad0..5af8acb55 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -436,7 +436,7 @@ package body Simul.Simulation.Main is if V then Nvec := (others => False); case Get_Kind (E.Stmt) is - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Nvec (0) := True; when others => @@ -483,7 +483,7 @@ package body Simul.Simulation.Main is (E.Instance, "psl assertion", E.Stmt, "assertion violation", 2); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => if Nvec (S_Num) then if Get_Report_Expression (E.Stmt) /= Null_Iir then Execute_Failed_Assertion @@ -569,7 +569,7 @@ package body Simul.Simulation.Main is (To_Instance_Acc (E'Address), PSL_Assert_Finalizer'Access); end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => -- TODO null; when others => diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb index 1e179c122..476598775 100644 --- a/src/vhdl/translate/trans-chap9.adb +++ b/src/vhdl/translate/trans-chap9.adb @@ -531,7 +531,7 @@ package body Trans.Chap9 is Assocs : O_Assoc_List; begin case Get_Kind (Stmt) is - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => Translate_Psl_Report (Stmt, Base, Report_Proc); when others => null; @@ -556,7 +556,7 @@ package body Trans.Chap9 is New_Var_Decl (Var_I, Wki_I, O_Storage_Local, Ghdl_Index_Type); Init_Var (Var_I); case Get_Kind (Stmt) is - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => -- Sequences for cover or endpoints are detected on every cycle, -- so the start state is always active. @@ -647,7 +647,7 @@ package body Trans.Chap9 is when Iir_Kind_Psl_Assert_Statement => Chap8.Translate_Report (Stmt, Ghdl_Psl_Assert_Failed, Severity_Level_Error); - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => if Get_Report_Expression (Stmt) /= Null_Iir then Start_Association (Assocs, Report_Proc); New_Association (Assocs, New_Obj_Value (Instance)); @@ -742,7 +742,7 @@ package body Trans.Chap9 is Info.Psl_Proc_Final_Subprg := O_Dnode_Null; end if; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => Create_Psl_Final_Proc (Stmt, Base, Instance); Start_Subprogram_Body (Info.Psl_Proc_Final_Subprg); @@ -975,7 +975,7 @@ package body Trans.Chap9 is when Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Translate_Psl_Directive_Declarations (El); when Iir_Kind_Component_Instantiation_Statement => @@ -1123,7 +1123,7 @@ package body Trans.Chap9 is when Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Translate_Psl_Directive_Statement (Stmt, Base_Info); when Iir_Kind_Component_Instantiation_Statement => @@ -2722,7 +2722,7 @@ package body Trans.Chap9 is | Iir_Kind_Psl_Endpoint_Declaration => null; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement => + | Iir_Kind_Psl_Cover_Directive => null; when Iir_Kind_Component_Instantiation_Statement => declare @@ -2784,7 +2784,7 @@ package body Trans.Chap9 is when Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Elab_Psl_Directive (Stmt, Base_Info); when Iir_Kind_Component_Instantiation_Statement => diff --git a/src/vhdl/translate/trans-rtis.adb b/src/vhdl/translate/trans-rtis.adb index e59a12b92..96aacb8b0 100644 --- a/src/vhdl/translate/trans-rtis.adb +++ b/src/vhdl/translate/trans-rtis.adb @@ -2040,7 +2040,7 @@ package body Trans.Rtis is Start_Init_Value (Info.Psl_Rti_Const); Start_Record_Aggr (List, Ghdl_Rtin_Object); case Get_Kind (Decl) is - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => Kind := Ghdl_Rtik_Psl_Cover; when Iir_Kind_Psl_Assert_Statement => Kind := Ghdl_Rtik_Psl_Assert; @@ -2423,7 +2423,7 @@ package body Trans.Rtis is when Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Generate_Psl_Directive (Stmt); when others => @@ -2995,7 +2995,7 @@ package body Trans.Rtis is | Iir_Kind_Sensitized_Process_Statement => return Node_Info.Process_Rti_Const; when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => return Node_Info.Psl_Rti_Const; when others => @@ -3036,7 +3036,7 @@ package body Trans.Rtis is | Iir_Kind_Sensitized_Process_Statement => Ref := Get_Instance_Ref (Node_Info.Process_Scope); when Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Endpoint_Declaration => Ref := Get_Instance_Ref (Node_Info.Psl_Scope); when others => diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index c6415c229..074ea4f15 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -1042,7 +1042,7 @@ package body Vhdl.Annotations is | Iir_Kind_Psl_Declaration => null; - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Assert_Statement | Iir_Kind_Psl_Restrict_Directive => null; diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index 8c8922fce..65ac4eb39 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -2141,7 +2141,7 @@ package body Vhdl.Canon is Canon_Psl_Directive (El); end; - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => Canon_Psl_Sequence_Directive (El); if Canon_Flag_Expressions then Canon_Expression (Get_Severity_Expression (El)); diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index 78a97605c..c4dd2f1b6 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -343,7 +343,7 @@ package body Vhdl.Elocations is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Case_Generate_Statement | Iir_Kind_Psl_Default_Clock diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index c104247c1..286ba751c 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -405,7 +405,7 @@ package Vhdl.Elocations is -- Iir_Kind_Psl_Default_Clock (None) -- Iir_Kind_Psl_Assert_Statement (None) - -- Iir_Kind_Psl_Cover_Statement (None) + -- Iir_Kind_Psl_Cover_Directive (None) -- Iir_Kind_Psl_Restrict_Directive (None) -- Iir_Kind_Component_Instantiation_Statement (L3) diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index e4c7ba93c..57be65311 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -689,7 +689,7 @@ package body Vhdl.Errors is return Disp_Label (Node, "concurrent assertion"); when Iir_Kind_Psl_Assert_Statement => return Disp_Label (Node, "PSL assertion"); - when Iir_Kind_Psl_Cover_Statement => + when Iir_Kind_Psl_Cover_Directive => return Disp_Label (Node, "PSL cover"); when Iir_Kind_Psl_Restrict_Directive => return "PSL restrict"; diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 70c62b692..dfb9629af 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1236,7 +1236,7 @@ package body Vhdl.Nodes is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_Component_Instantiation_Statement diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 5d8c902b1..fa376c795 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -2887,14 +2887,14 @@ package Vhdl.Nodes is -- Get/Set_Identifier (Alias Field3) -- Iir_Kind_Psl_Assert_Statement (Medium) - -- Iir_Kind_Psl_Cover_Statement (Medium) + -- Iir_Kind_Psl_Cover_Directive (Medium) -- -- Get/Set_Parent (Field0) -- -- Only for Iir_Kind_Psl_Assert_Statement: -- Get/Set_Psl_Property (Field1) -- - -- Only for Iir_Kind_Psl_Cover_Statement: + -- Only for Iir_Kind_Psl_Cover_Directive: -- Get/Set_Psl_Sequence (Field1) -- -- Get/Set_Chain (Field2) @@ -4361,7 +4361,7 @@ package Vhdl.Nodes is Iir_Kind_Concurrent_Assertion_Statement, Iir_Kind_Concurrent_Procedure_Call_Statement, Iir_Kind_Psl_Assert_Statement, - Iir_Kind_Psl_Cover_Statement, + Iir_Kind_Psl_Cover_Directive, Iir_Kind_Psl_Restrict_Directive, Iir_Kind_Block_Statement, Iir_Kind_If_Generate_Statement, @@ -5534,7 +5534,7 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Assertion_Statement --Iir_Kind_Concurrent_Procedure_Call_Statement --Iir_Kind_Psl_Assert_Statement - --Iir_Kind_Psl_Cover_Statement + --Iir_Kind_Psl_Cover_Directive --Iir_Kind_Psl_Restrict_Directive --Iir_Kind_Block_Statement --Iir_Kind_If_Generate_Statement @@ -5552,7 +5552,7 @@ package Vhdl.Nodes is --Iir_Kind_Concurrent_Assertion_Statement --Iir_Kind_Concurrent_Procedure_Call_Statement --Iir_Kind_Psl_Assert_Statement - --Iir_Kind_Psl_Cover_Statement + --Iir_Kind_Psl_Cover_Directive Iir_Kind_Psl_Restrict_Directive; subtype Iir_Kinds_Concurrent_Signal_Assignment is Iir_Kind range diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 712d0fa81..48c5129bc 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -1390,8 +1390,8 @@ package body Vhdl.Nodes_Meta is return "concurrent_procedure_call_statement"; when Iir_Kind_Psl_Assert_Statement => return "psl_assert_statement"; - when Iir_Kind_Psl_Cover_Statement => - return "psl_cover_statement"; + when Iir_Kind_Psl_Cover_Directive => + return "psl_cover_directive"; when Iir_Kind_Psl_Restrict_Directive => return "psl_restrict_directive"; when Iir_Kind_Block_Statement => @@ -3809,7 +3809,7 @@ package body Vhdl.Nodes_Meta is Field_Severity_Expression, Field_Report_Expression, Field_PSL_Clock_Sensitivity, - -- Iir_Kind_Psl_Cover_Statement + -- Iir_Kind_Psl_Cover_Directive Field_Psl_Sequence, Field_Label, Field_PSL_Clock, @@ -4641,7 +4641,7 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Concurrent_Assertion_Statement => 1378, Iir_Kind_Concurrent_Procedure_Call_Statement => 1385, Iir_Kind_Psl_Assert_Statement => 1398, - Iir_Kind_Psl_Cover_Statement => 1411, + Iir_Kind_Psl_Cover_Directive => 1411, Iir_Kind_Psl_Restrict_Directive => 1422, Iir_Kind_Block_Statement => 1436, Iir_Kind_If_Generate_Statement => 1447, @@ -7394,7 +7394,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement @@ -8173,7 +8173,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement @@ -8224,7 +8224,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement @@ -8310,7 +8310,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement @@ -8778,7 +8778,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -9036,7 +9036,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Assertion_Statement | Iir_Kind_Report_Statement => return True; @@ -9050,7 +9050,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Assertion_Statement | Iir_Kind_Report_Statement => return True; @@ -9394,7 +9394,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement | Iir_Kind_If_Generate_Statement @@ -10753,7 +10753,7 @@ package body Vhdl.Nodes_Meta is function Has_Psl_Sequence (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Psl_Cover_Statement + when Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -10788,7 +10788,7 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -10802,7 +10802,7 @@ package body Vhdl.Nodes_Meta is when Iir_Kind_Psl_Declaration | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -10815,7 +10815,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -10828,7 +10828,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => @@ -10841,7 +10841,7 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Psl_Assert_Statement - | Iir_Kind_Psl_Cover_Statement + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive => return True; when others => diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index c049f1ece..e5ff0292a 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -8608,7 +8608,7 @@ package body Vhdl.Parse is is Res : Iir; begin - Res := Create_Iir (Iir_Kind_Psl_Cover_Statement); + Res := Create_Iir (Iir_Kind_Psl_Cover_Directive); -- Skip 'cover' Scan; diff --git a/src/vhdl/vhdl-prints.adb b/src/vhdl/vhdl-prints.adb index 2d14bbc2a..46e12a2e3 100644 --- a/src/vhdl/vhdl-prints.adb +++ b/src/vhdl/vhdl-prints.adb @@ -3889,7 +3889,7 @@ package body Vhdl.Prints is Disp_PSL_NFA (Get_PSL_NFA (Stmt)); end Disp_Psl_Assert_Statement; - procedure Disp_Psl_Cover_Statement + procedure Disp_Psl_Cover_Directive (Ctxt : in out Ctxt_Class; Stmt : Iir) is begin if Vhdl_Std < Vhdl_08 then @@ -3902,7 +3902,7 @@ package body Vhdl.Prints is Disp_Token (Ctxt, Tok_Semi_Colon); Close_Hbox (Ctxt); Disp_PSL_NFA (Get_PSL_NFA (Stmt)); - end Disp_Psl_Cover_Statement; + end Disp_Psl_Cover_Directive; procedure Disp_Psl_Restrict_Directive (Ctxt : in out Ctxt_Class; Stmt : Iir) is @@ -3964,8 +3964,8 @@ package body Vhdl.Prints is Disp_Psl_Declaration (Ctxt, Stmt); when Iir_Kind_Psl_Assert_Statement => Disp_Psl_Assert_Statement (Ctxt, Stmt); - when Iir_Kind_Psl_Cover_Statement => - Disp_Psl_Cover_Statement (Ctxt, Stmt); + when Iir_Kind_Psl_Cover_Directive => + Disp_Psl_Cover_Directive (Ctxt, Stmt); when Iir_Kind_Psl_Restrict_Directive => Disp_Psl_Restrict_Directive (Ctxt, Stmt); when Iir_Kind_Simple_Simultaneous_Statement => @@ -4282,8 +4282,8 @@ package body Vhdl.Prints is | Iir_Kind_Indexed_Name | Iir_Kind_Slice_Name => Print (Ctxt, N); - when Iir_Kind_Psl_Cover_Statement => - Disp_Psl_Cover_Statement (Ctxt, N); + when Iir_Kind_Psl_Cover_Directive => + Disp_Psl_Cover_Directive (Ctxt, N); when others => Error_Kind ("disp", N); end case; diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index 4fd0ab2e4..b4e949aac 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -732,7 +732,7 @@ package body Vhdl.Sem_Psl is return Stmt; end Sem_Psl_Assert_Statement; - procedure Sem_Psl_Cover_Statement (Stmt : Iir) + procedure Sem_Psl_Cover_Directive (Stmt : Iir) is Seq : PSL_Node; begin @@ -748,7 +748,7 @@ package body Vhdl.Sem_Psl is -- Check simple subset restrictions. PSL.Subsets.Check_Simple (Seq); - end Sem_Psl_Cover_Statement; + end Sem_Psl_Cover_Directive; procedure Sem_Psl_Restrict_Directive (Stmt : Iir) is diff --git a/src/vhdl/vhdl-sem_psl.ads b/src/vhdl/vhdl-sem_psl.ads index e4d9c5de1..433555b20 100644 --- a/src/vhdl/vhdl-sem_psl.ads +++ b/src/vhdl/vhdl-sem_psl.ads @@ -25,7 +25,7 @@ package Vhdl.Sem_Psl is -- May return a non-psl concurrent assertion statement. function Sem_Psl_Assert_Statement (Stmt : Iir) return Iir; - procedure Sem_Psl_Cover_Statement (Stmt : Iir); + procedure Sem_Psl_Cover_Directive (Stmt : Iir); procedure Sem_Psl_Restrict_Directive (Stmt : Iir); procedure Sem_Psl_Default_Clock (Stmt : Iir); function Sem_Psl_Name (Name : Iir) return Iir; diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb index 5e9ca55ba..02db8418a 100644 --- a/src/vhdl/vhdl-sem_stmts.adb +++ b/src/vhdl/vhdl-sem_stmts.adb @@ -2019,8 +2019,8 @@ package body Vhdl.Sem_Stmts is Sem_Psl.Sem_Psl_Endpoint_Declaration (El); when Iir_Kind_Psl_Assert_Statement => New_El := Sem_Psl.Sem_Psl_Assert_Statement (El); - when Iir_Kind_Psl_Cover_Statement => - Sem_Psl.Sem_Psl_Cover_Statement (El); + when Iir_Kind_Psl_Cover_Directive => + Sem_Psl.Sem_Psl_Cover_Directive (El); when Iir_Kind_Psl_Restrict_Directive => Sem_Psl.Sem_Psl_Restrict_Directive (El); when Iir_Kind_Psl_Default_Clock => |