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| author | Tristan Gingold <tgingold@free.fr> | 2016-12-17 18:10:22 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-12-17 18:10:22 +0100 |
| commit | 680ea916dee2f5aadeeb5f507ea918598803aca8 (patch) | |
| tree | cf48e8c6e56446e0442735aac1a95d66c4772c6c /src/vhdl | |
| parent | 4e7d32ee912d21188cf07fd03cc343869139ba52 (diff) | |
| download | ghdl-680ea916dee2f5aadeeb5f507ea918598803aca8.tar.gz ghdl-680ea916dee2f5aadeeb5f507ea918598803aca8.tar.bz2 ghdl-680ea916dee2f5aadeeb5f507ea918598803aca8.zip | |
disp_vhdl: add -do flag to display evaluated expressions.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/disp_vhdl.adb | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/vhdl/disp_vhdl.adb b/src/vhdl/disp_vhdl.adb index c00565515..64e38eada 100644 --- a/src/vhdl/disp_vhdl.adb +++ b/src/vhdl/disp_vhdl.adb @@ -303,7 +303,7 @@ package body Disp_Vhdl is declare Origin : constant Iir := Get_Range_Origin (Rng); begin - if Origin /= Null_Iir then + if Dump_Origin_Flag and then Origin /= Null_Iir then Disp_Expression (Origin); else Disp_Expression (Get_Left_Limit (Rng)); @@ -2649,21 +2649,21 @@ package body Disp_Vhdl is case Get_Kind (Expr) is when Iir_Kind_Integer_Literal => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_Int64 (Get_Value (Expr)); end if; when Iir_Kind_Floating_Point_Literal => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_Fp64 (Get_Fp_Value (Expr)); end if; when Iir_Kind_String_Literal8 => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_String_Literal @@ -2677,7 +2677,7 @@ package body Disp_Vhdl is when Iir_Kind_Physical_Fp_Literal | Iir_Kind_Physical_Int_Literal => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_Physical_Literal (Expr); @@ -2688,14 +2688,14 @@ package body Disp_Vhdl is Disp_Identifier (Expr); when Iir_Kind_Enumeration_Literal => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_Name_Of (Expr); end if; when Iir_Kind_Overflow_Literal => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Put ("*OVERFLOW*"); @@ -2709,7 +2709,7 @@ package body Disp_Vhdl is Put ("null"); when Iir_Kind_Simple_Aggregate => Orig := Get_Literal_Origin (Expr); - if Orig /= Null_Iir then + if Dump_Origin_Flag and then Orig /= Null_Iir then Disp_Expression (Orig); else Disp_Simple_Aggregate (Expr); |