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authorTristan Gingold <tgingold@free.fr>2021-09-22 19:41:14 +0200
committerTristan Gingold <tgingold@free.fr>2021-09-23 04:43:13 +0200
commit565967d1328237bea7da40b99efd03ac1f326abd (patch)
tree51e2ca95a4a912e94f11c7aebd86014e1ff1691b /src/vhdl
parented130382d50b96f80e2fb498728564db1468c943 (diff)
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vhdl-ieee-vital_timing.adb: handle vhdl 2008. Fix #1875
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/vhdl-ieee-vital_timing.adb18
1 files changed, 15 insertions, 3 deletions
diff --git a/src/vhdl/vhdl-ieee-vital_timing.adb b/src/vhdl/vhdl-ieee-vital_timing.adb
index 57d97c0ea..945c7ee0a 100644
--- a/src/vhdl/vhdl-ieee-vital_timing.adb
+++ b/src/vhdl/vhdl-ieee-vital_timing.adb
@@ -13,13 +13,16 @@
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <gnu.org/licenses>.
+
with Types; use Types;
with Std_Names;
+with Flags; use Flags;
with Errorout; use Errorout;
+with Name_Table;
+
with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Std_Package; use Vhdl.Std_Package;
with Vhdl.Tokens; use Vhdl.Tokens;
-with Name_Table;
with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164;
with Vhdl.Sem_Scopes;
with Vhdl.Sem_Specs;
@@ -218,6 +221,15 @@ package body Vhdl.Ieee.Vital_Timing is
end case;
end Check_Level0_Attribute_Specification;
+ function Is_Slv_Subtype (Base_Type : Iir) return Boolean is
+ begin
+ if Vhdl_Std >= Vhdl_08 then
+ return Base_Type = Std_Ulogic_Vector_Type;
+ else
+ return Base_Type = Std_Logic_Vector_Type;
+ end if;
+ end Is_Slv_Subtype;
+
procedure Check_Entity_Port_Declaration
(Decl : Iir_Interface_Signal_Declaration)
is
@@ -260,7 +272,7 @@ package body Vhdl.Ieee.Vital_Timing is
Atype := Get_Type (Decl);
Base_Type := Get_Base_Type (Atype);
Type_Decl := Get_Type_Declarator (Atype);
- if Base_Type = Std_Logic_Vector_Type then
+ if Is_Slv_Subtype (Base_Type) then
if Get_Resolution_Indication (Atype) /= Null_Iir then
Error_Vital
(+Decl,
@@ -562,7 +574,7 @@ package body Vhdl.Ieee.Vital_Timing is
if Get_Base_Type (Ptype) = Std_Ulogic_Type then
return Port_Length_Scalar;
elsif Get_Kind (Ptype) = Iir_Kind_Array_Subtype_Definition
- and then Get_Base_Type (Ptype) = Std_Logic_Vector_Type
+ and then Is_Slv_Subtype (Get_Base_Type (Ptype))
then
Itype := Get_Nth_Element (Get_Index_Subtype_List (Ptype), 0);
if Get_Type_Staticness (Itype) /= Locally then