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author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:26:50 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:27:12 +0100 |
commit | 493fe4337300dbcfd796715bd7268347ba849950 (patch) | |
tree | 9bb516d249d51eb4e1f1cfa6cb531898a4ccc82c /src/vhdl | |
parent | 26aefc178f1f2d1eee9f0e48d919adb56b274466 (diff) | |
download | ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.gz ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.bz2 ghdl-493fe4337300dbcfd796715bd7268347ba849950.zip |
vhdl: recognize conversion functions from std_logic_1164
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 43 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
2 files changed, 49 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index be78f6afc..6947cb612 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -35,6 +35,13 @@ package body Vhdl.Ieee.Std_Logic_1164 is or Base_Type = Std_Logic_Vector_Type; end Is_Vector_Parameter; + function Is_Bitvec_Parameter (Inter : Iir) return Boolean + is + Base_Type : constant Iir := Get_Base_Type (Get_Type (Inter)); + begin + return Base_Type = Std_Package.Bit_Vector_Type_Definition; + end Is_Bitvec_Parameter; + function Is_Integer_Parameter (Inter : Iir) return Boolean is begin return (Get_Base_Type (Get_Type (Inter)) @@ -147,6 +154,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is return True; end Is_Vector_Function; + -- Return True iff the profile of FUNC is: (l : bit_vector) + function Is_Bitvec_Function (Func : Iir) return Boolean + is + Inter : constant Iir := Get_Interface_Declaration_Chain (Func); + begin + if Get_Implicit_Definition (Func) /= Iir_Predefined_None then + return False; + end if; + if Inter = Null_Iir or else not Is_Bitvec_Parameter (Inter) then + return False; + end if; + if Get_Chain (Inter) /= Null_Iir then + return False; + end if; + + return True; + end Is_Bitvec_Function; + procedure Extract_Declarations (Pkg : Iir_Package_Declaration) is Error : exception; @@ -277,6 +302,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is (Get_Interface_Declaration_Chain (Decl), False); when Name_To_Bitvector => Predefined := Iir_Predefined_Ieee_1164_To_Bitvector; + when Name_To_Stdulogic => + Predefined := Iir_Predefined_Ieee_1164_To_Stdulogic; + when Name_To_Stdlogicvector => + if Is_Vector_Function (Decl) then + Predefined := + Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv; + elsif Is_Bitvec_Function (Decl) then + Predefined := + Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv; + end if; + when Name_To_Stdulogicvector => + if Is_Vector_Function (Decl) then + Predefined := + Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv; + elsif Is_Bitvec_Function (Decl) then + Predefined := + Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv; + end if; when others => if Is_Scalar_Scalar_Function (Decl) then case Get_Identifier (Decl) is diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 44618964c..104cf529a 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5444,7 +5444,13 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Vector_Xnor, Iir_Predefined_Ieee_1164_Vector_Not, + Iir_Predefined_Ieee_1164_To_Bit, Iir_Predefined_Ieee_1164_To_Bitvector, + Iir_Predefined_Ieee_1164_To_Stdulogic, + Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv, + Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv, + Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv, + Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv, Iir_Predefined_Ieee_1164_Vector_Is_X, Iir_Predefined_Ieee_1164_Scalar_Is_X, |