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author | Tristan Gingold <tgingold@free.fr> | 2017-11-16 05:20:04 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-11-16 05:20:04 +0100 |
commit | 41ba0f0fe89032eba308eef964bc6235fefa065f (patch) | |
tree | 479243bb0d4e9b2b50123179816be78a699dfe08 /src/vhdl | |
parent | 349fd0f7c940d11b4d4d6ee5b5e5d4f070896140 (diff) | |
download | ghdl-41ba0f0fe89032eba308eef964bc6235fefa065f.tar.gz ghdl-41ba0f0fe89032eba308eef964bc6235fefa065f.tar.bz2 ghdl-41ba0f0fe89032eba308eef964bc6235fefa065f.zip |
simulate: add port map.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/simulate/elaboration.adb | 41 | ||||
-rw-r--r-- | src/vhdl/simulate/elaboration.ads | 3 | ||||
-rw-r--r-- | src/vhdl/simulate/execution.adb | 1 |
3 files changed, 29 insertions, 16 deletions
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 243f9fce9..136fb30bb 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -350,6 +350,7 @@ package body Elaboration is Parent => Father, Children => null, Brother => null, + Ports_Map => Null_Iir, Marker => Empty_Marker, Objects => (others => null), Elab_Objects => 0, @@ -1246,6 +1247,9 @@ package body Elaboration is Actual : Iir; Formal : Iir; begin + pragma Assert (Formal_Instance.Ports_Map = Null_Iir); + Formal_Instance.Ports_Map := Map; + if Ports = Null_Iir then return; end if; @@ -2138,27 +2142,32 @@ package body Elaboration is Item : Iir; begin - -- Gather block children. + -- Gather children and reverse the list. declare - Child : Block_Instance_Acc; - Child_Info : Sim_Info_Acc; + Child, Prev, First : Block_Instance_Acc; begin Child := Instance.Children; + First := null; while Child /= null loop - Child_Info := Get_Info (Child.Label); - if Child_Info.Kind = Kind_Block then - declare - Slot : constant Instance_Slot_Type := Child_Info.Inst_Slot; - begin - -- Skip processes (they have no slot). - if Slot /= Invalid_Instance_Slot then - pragma Assert (Sub_Instances (Slot) = null); - Sub_Instances (Slot) := Child; - end if; - end; - end if; - Child := Child.Brother; + declare + Slot : constant Instance_Slot_Type := + Get_Info (Child.Label).Inst_Slot; + begin + -- Skip processes (they have no slot). + if Slot /= Invalid_Instance_Slot then + pragma Assert (Sub_Instances (Slot) = null); + Sub_Instances (Slot) := Child; + end if; + end; + + -- Reverse + Prev := Child.Brother; + Child.Brother := First; + First := Child; + + Child := Prev; end loop; + Instance.Children := First; end; -- Associate configuration items with subinstance. Gather items for diff --git a/src/vhdl/simulate/elaboration.ads b/src/vhdl/simulate/elaboration.ads index 9a03bcc25..992f81716 100644 --- a/src/vhdl/simulate/elaboration.ads +++ b/src/vhdl/simulate/elaboration.ads @@ -80,6 +80,9 @@ package Elaboration is Children: Block_Instance_Acc; Brother: Block_Instance_Acc; + -- Port association map for this block, if any. + Ports_Map : Iir; + -- Pool marker for the child (only for subprograms and processes). Marker : Areapools.Mark_Type; diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/execution.adb index f5aa56073..2ecf13ffb 100644 --- a/src/vhdl/simulate/execution.adb +++ b/src/vhdl/simulate/execution.adb @@ -3302,6 +3302,7 @@ package body Execution is Parent => Instance, Children => null, Brother => null, + Ports_Map => Null_Iir, Marker => Empty_Marker, Objects => (others => null), Elab_Objects => 0, |