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| author | Tristan Gingold <tgingold@free.fr> | 2015-09-03 20:20:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2015-09-03 20:20:24 +0200 |
| commit | 2d8f611cb63b72aa0373efe0ffa0df47e25519c9 (patch) | |
| tree | 50d675079beccf64f6856193266cce9508fff0a0 /src/vhdl | |
| parent | 26af2bf1ad5f949e05d0e3ac560bbd22e41d7158 (diff) | |
| download | ghdl-2d8f611cb63b72aa0373efe0ffa0df47e25519c9.tar.gz ghdl-2d8f611cb63b72aa0373efe0ffa0df47e25519c9.tar.bz2 ghdl-2d8f611cb63b72aa0373efe0ffa0df47e25519c9.zip | |
Adjust previous patch (destroy types for default port values).
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/translate/trans-chap4.adb | 14 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap5.adb | 6 |
2 files changed, 13 insertions, 7 deletions
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb index 848daf8f0..70f41651b 100644 --- a/src/vhdl/translate/trans-chap4.adb +++ b/src/vhdl/translate/trans-chap4.adb @@ -26,6 +26,7 @@ with Trans.Chap3; with Trans.Chap5; with Trans.Chap6; with Trans.Chap7; +with Trans.Chap9; with Trans.Chap14; with Trans.Rtis; with Trans.Helpers2; use Trans.Helpers2; @@ -1002,7 +1003,7 @@ package body Trans.Chap4 is Sig_Type : constant Iir := Get_Type (Sig); Base_Decl : constant Iir := Get_Object_Prefix (Sig); Name_Node : Mnode; - Val : Iir; + Value : Iir; Data : Elab_Signal_Data; begin New_Debug_Line_Stmt (Get_Line_Number (Sig)); @@ -1030,12 +1031,12 @@ package body Trans.Chap4 is if Decl = Base_Decl then Data.Already_Resolved := False; Data.Check_Null := Check_Null; - Val := Get_Default_Value (Base_Decl); - if Val = Null_Iir then + Value := Get_Default_Value (Base_Decl); + if Value = Null_Iir then Data.Has_Val := False; else Data.Has_Val := True; - Data.Val := E2M (Chap7.Translate_Expression (Val, Sig_Type), + Data.Val := E2M (Chap7.Translate_Expression (Value, Sig_Type), Get_Info (Sig_Type), Mode_Value); end if; @@ -1046,10 +1047,15 @@ package body Trans.Chap4 is Data.Already_Resolved := True; Data.Has_Val := False; Data.Check_Null := False; + Value := Null_Iir; end if; Elab_Signal (Name_Node, Sig_Type, Data); Close_Temp; + + if Value /= Null_Iir then + Chap9.Destroy_Types (Value); + end if; end Elab_Signal_Declaration_Object; procedure Elab_Signal_Declaration diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index 7897d8e2e..47950b737 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -643,18 +643,18 @@ package body Trans.Chap5 is end if; when Iir_Kind_Association_Element_Open => declare - Actual_Type : Iir; + Value : constant Iir := Get_Default_Value (Formal_Base); + Actual_Type : constant Iir := Get_Type (Value); Bounds : Mnode; Formal_Node : Mnode; begin - Actual_Type := - Get_Type (Get_Default_Value (Formal_Base)); Chap3.Create_Array_Subtype (Actual_Type); Bounds := Chap3.Get_Array_Type_Bounds (Actual_Type); Formal_Node := Chap6.Translate_Name (Formal); New_Assign_Stmt (M2Lp (Chap3.Get_Array_Bounds (Formal_Node)), M2Addr (Bounds)); + Chap9.Destroy_Types (Value); end; when Iir_Kind_Association_Element_By_Individual => declare |