disp_vhdl: handle psl default clock in declarative part.

2 files changed, 63 insertions, 56 deletions

diff --git a/src/vhdl/disp_vhdl.adb b/src/vhdl/disp_vhdl.adb
index cd279ecfd..f3e8c8f37 100644
--- a/src/vhdl/disp_vhdl.adb
+++ b/src/vhdl/disp_vhdl.adb
@@ -1700,6 +1700,66 @@ package body Disp_Vhdl is
       Put_Line (");");
    end Disp_Group_Declaration;
 
+   procedure Disp_PSL_HDL_Expr (N : PSL.Nodes.HDL_Node) is
+   begin
+      Disp_Expression (Iir (N));
+   end Disp_PSL_HDL_Expr;
+
+   procedure Disp_Psl_Expression (Expr : PSL_Node) is
+   begin
+      PSL.Prints.HDL_Expr_Printer := Disp_PSL_HDL_Expr'Access;
+      PSL.Prints.Print_Property (Expr);
+   end Disp_Psl_Expression;
+
+   procedure Disp_Psl_Sequence (Expr : PSL_Node) is
+   begin
+      PSL.Prints.HDL_Expr_Printer := Disp_PSL_HDL_Expr'Access;
+      PSL.Prints.Print_Sequence (Expr);
+   end Disp_Psl_Sequence;
+
+   procedure Disp_Psl_Default_Clock (Stmt : Iir) is
+   begin
+      if Vhdl_Std < Vhdl_08 then
+         Put ("--psl ");
+      end if;
+      Put ("default clock is ");
+      Disp_Psl_Expression (Get_Psl_Boolean (Stmt));
+      Put_Line (";");
+   end Disp_Psl_Default_Clock;
+
+   procedure Disp_Psl_Declaration (Stmt : Iir)
+   is
+      use PSL.Nodes;
+      Decl : constant PSL_Node := Get_Psl_Declaration (Stmt);
+   begin
+      if Vhdl_Std < Vhdl_08 then
+         Put ("--psl ");
+      end if;
+      case Get_Kind (Decl) is
+         when N_Property_Declaration =>
+            Put ("property ");
+            Disp_Ident (Get_Identifier (Decl));
+            Put (" is ");
+            Disp_Psl_Expression (Get_Property (Decl));
+            Put_Line (";");
+         when N_Sequence_Declaration =>
+            Put ("sequence ");
+            Disp_Ident (Get_Identifier (Decl));
+            Put (" is ");
+            Disp_Psl_Sequence (Get_Sequence (Decl));
+            Put_Line (";");
+         when N_Endpoint_Declaration =>
+            Put ("endpoint ");
+            Disp_Ident (Get_Identifier (Decl));
+            Put (" is ");
+            Disp_Psl_Sequence (Get_Sequence (Decl));
+            Put_Line (";");
+            Disp_PSL_NFA (Get_PSL_NFA (Stmt));
+         when others =>
+            Error_Kind ("disp_psl_declaration", Decl);
+      end case;
+   end Disp_Psl_Declaration;
+
    procedure Disp_Declaration_Chain (Parent : Iir; Indent: Count)
    is
       Decl: Iir;
@@ -1770,6 +1830,8 @@ package body Disp_Vhdl is
                Disp_Package_Body (Decl);
             when Iir_Kind_Package_Instantiation_Declaration =>
                Disp_Package_Instantiation_Declaration (Decl);
+            when Iir_Kind_Psl_Default_Clock =>
+               Disp_Psl_Default_Clock (Decl);
             when others =>
                Error_Kind ("disp_declaration_chain", Decl);
          end case;
@@ -2913,23 +2975,6 @@ package body Disp_Vhdl is
       end case;
    end Disp_Expression;
 
-   procedure Disp_PSL_HDL_Expr (N : PSL.Nodes.HDL_Node) is
-   begin
-      Disp_Expression (Iir (N));
-   end Disp_PSL_HDL_Expr;
-
-   procedure Disp_Psl_Expression (Expr : PSL_Node) is
-   begin
-      PSL.Prints.HDL_Expr_Printer := Disp_PSL_HDL_Expr'Access;
-      PSL.Prints.Print_Property (Expr);
-   end Disp_Psl_Expression;
-
-   procedure Disp_Psl_Sequence (Expr : PSL_Node) is
-   begin
-      PSL.Prints.HDL_Expr_Printer := Disp_PSL_HDL_Expr'Access;
-      PSL.Prints.Print_Sequence (Expr);
-   end Disp_Psl_Sequence;
-
    procedure Disp_Block_Header (Header : Iir_Block_Header; Indent: Count)
    is
       Chain : Iir;
@@ -3095,44 +3140,6 @@ package body Disp_Vhdl is
       Disp_End (Stmt, "generate");
    end Disp_Case_Generate_Statement;
 
-   procedure Disp_Psl_Default_Clock (Stmt : Iir) is
-   begin
-      Put ("--psl default clock is ");
-      Disp_Psl_Expression (Get_Psl_Boolean (Stmt));
-      Put_Line (";");
-   end Disp_Psl_Default_Clock;
-
-   procedure Disp_Psl_Declaration (Stmt : Iir)
-   is
-      use PSL.Nodes;
-      Decl : constant PSL_Node := Get_Psl_Declaration (Stmt);
-   begin
-      Put ("--psl ");
-      case Get_Kind (Decl) is
-         when N_Property_Declaration =>
-            Put ("property ");
-            Disp_Ident (Get_Identifier (Decl));
-            Put (" is ");
-            Disp_Psl_Expression (Get_Property (Decl));
-            Put_Line (";");
-         when N_Sequence_Declaration =>
-            Put ("sequence ");
-            Disp_Ident (Get_Identifier (Decl));
-            Put (" is ");
-            Disp_Psl_Sequence (Get_Sequence (Decl));
-            Put_Line (";");
-         when N_Endpoint_Declaration =>
-            Put ("endpoint ");
-            Disp_Ident (Get_Identifier (Decl));
-            Put (" is ");
-            Disp_Psl_Sequence (Get_Sequence (Decl));
-            Put_Line (";");
-            Disp_PSL_NFA (Get_PSL_NFA (Stmt));
-         when others =>
-            Error_Kind ("disp_psl_declaration", Decl);
-      end case;
-   end Disp_Psl_Declaration;
-
    procedure Disp_PSL_NFA (N : PSL.Nodes.NFA)
    is
       use PSL.NFAs;
diff --git a/src/vhdl/iirs.ads b/src/vhdl/iirs.ads
index cc3237398..277aa1bcd 100644
--- a/src/vhdl/iirs.ads
+++ b/src/vhdl/iirs.ads
@@ -5164,7 +5164,7 @@ package Iirs is
      Iir_Kind_Base_Attribute ..
      Iir_Kind_Reverse_Range_Array_Attribute;
 
-   --  Attributes of a scalar type.
+   --  Attributes of scalar types.
    subtype Iir_Kinds_Type_Attribute is Iir_Kind range
      Iir_Kind_Left_Type_Attribute ..
    --Iir_Kind_Right_Type_Attribute