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authorTristan Gingold <tgingold@free.fr>2020-06-24 07:47:03 +0200
committerTristan Gingold <tgingold@free.fr>2020-06-24 21:41:07 +0200
commitb85a4d387b378d3b15e115293c0bf01728229f52 (patch)
tree28ceb5ecfa9f1790643e40c442458edd24969a2e /src/vhdl/vhdl-sem_names.adb
parente359f04bdaa8b5cad3846d333f9dedf4df62c1ef (diff)
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vhdl/translate: rework object type elaboration. For #641
Diffstat (limited to 'src/vhdl/vhdl-sem_names.adb')
-rw-r--r--src/vhdl/vhdl-sem_names.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb
index 7f1766b5b..9463b1b37 100644
--- a/src/vhdl/vhdl-sem_names.adb
+++ b/src/vhdl/vhdl-sem_names.adb
@@ -3630,7 +3630,7 @@ package body Vhdl.Sem_Names is
-- The type defined by 'subtype is always constrained. Create
-- a subtype if it is not.
Attr_Type := Get_Type (Prefix_Name);
- if False then
+ if not Is_Fully_Constrained_Type (Attr_Type) then
Attr_Type := Sem_Types.Build_Constrained_Subtype (Attr_Type, Attr);
end if;