From b85a4d387b378d3b15e115293c0bf01728229f52 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 24 Jun 2020 07:47:03 +0200
Subject: vhdl/translate: rework object type elaboration.  For #641

---
 src/vhdl/vhdl-sem_names.adb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/vhdl/vhdl-sem_names.adb')

diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb
index 7f1766b5b..9463b1b37 100644
--- a/src/vhdl/vhdl-sem_names.adb
+++ b/src/vhdl/vhdl-sem_names.adb
@@ -3630,7 +3630,7 @@ package body Vhdl.Sem_Names is
       --  The type defined by 'subtype is always constrained.  Create
       --  a subtype if it is not.
       Attr_Type := Get_Type (Prefix_Name);
-      if False then
+      if not Is_Fully_Constrained_Type (Attr_Type) then
          Attr_Type := Sem_Types.Build_Constrained_Subtype (Attr_Type, Attr);
       end if;
 
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