vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662

1 files changed, 7 insertions, 1 deletions

diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads
index bb0b4e102..25673bf8e 100644
--- a/src/vhdl/vhdl-nodes_meta.ads
+++ b/src/vhdl/vhdl-nodes_meta.ads
@@ -421,7 +421,10 @@ package Vhdl.Nodes_Meta is
       Field_PSL_NFA,
       Field_PSL_Nbr_States,
       Field_PSL_Clock_Sensitivity,
-      Field_PSL_EOS_Flag
+      Field_PSL_EOS_Flag,
+      Field_Count_Expression,
+      Field_Clock_Expression,
+      Field_Clock
      );
    pragma Discard_Names (Fields_Enum);
 
@@ -994,4 +997,7 @@ package Vhdl.Nodes_Meta is
    function Has_PSL_Nbr_States (K : Iir_Kind) return Boolean;
    function Has_PSL_Clock_Sensitivity (K : Iir_Kind) return Boolean;
    function Has_PSL_EOS_Flag (K : Iir_Kind) return Boolean;
+   function Has_Count_Expression (K : Iir_Kind) return Boolean;
+   function Has_Clock_Expression (K : Iir_Kind) return Boolean;
+   function Has_Clock (K : Iir_Kind) return Boolean;
 end Vhdl.Nodes_Meta;