From ad74ac7886532dd1a846712c92266158c8947589 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 1 Dec 2020 20:37:07 +0100 Subject: vhdl: recognize logica vec/log and log/vec operators. For #1520 --- src/vhdl/vhdl-nodes.ads | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/vhdl/vhdl-nodes.ads') diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index e6a9c3534..8e1d98c0b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5595,6 +5595,20 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, + -- VHDL-2008 vector/element logic operators + Iir_Predefined_Ieee_1164_And_Suv_Log, + Iir_Predefined_Ieee_1164_And_Log_Suv, + Iir_Predefined_Ieee_1164_Nand_Suv_Log, + Iir_Predefined_Ieee_1164_Nand_Log_Suv, + Iir_Predefined_Ieee_1164_Or_Suv_Log, + Iir_Predefined_Ieee_1164_Or_Log_Suv, + Iir_Predefined_Ieee_1164_Nor_Suv_Log, + Iir_Predefined_Ieee_1164_Nor_Log_Suv, + Iir_Predefined_Ieee_1164_Xor_Suv_Log, + Iir_Predefined_Ieee_1164_Xor_Log_Suv, + Iir_Predefined_Ieee_1164_Xnor_Suv_Log, + Iir_Predefined_Ieee_1164_Xnor_Log_Suv, + -- VHDL-2008 unary logic operators Iir_Predefined_Ieee_1164_And_Suv, Iir_Predefined_Ieee_1164_Nand_Suv, -- cgit v1.2.3