synth: handle more operations from synsopsys packages.

4 files changed, 142 insertions, 108 deletions

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 82baa62c8..1485d5ec2 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1361,86 +1361,88 @@ class Iir_Predefined:
     Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 378
     Ieee_Std_Logic_Unsigned_Add_Slv_Int = 379
     Ieee_Std_Logic_Unsigned_Add_Int_Slv = 380
-    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 381
-    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 382
+    Ieee_Std_Logic_Unsigned_Add_Slv_Log = 381
+    Ieee_Std_Logic_Unsigned_Add_Log_Slv = 382
     Ieee_Std_Logic_Unsigned_Sub_Slv_Slv = 383
     Ieee_Std_Logic_Unsigned_Sub_Slv_Int = 384
     Ieee_Std_Logic_Unsigned_Sub_Int_Slv = 385
-    Ieee_Std_Logic_Unsigned_Sub_Slv_Sl = 386
-    Ieee_Std_Logic_Unsigned_Sub_Sl_Slv = 387
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 388
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 389
-    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 390
-    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 391
-    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 392
-    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 393
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 394
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 395
-    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 396
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 397
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 398
-    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 399
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 400
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 401
-    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 402
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 403
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 404
-    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 405
-    Ieee_Std_Logic_Unsigned_Conv_Integer = 406
-    Ieee_Std_Logic_Signed_Add_Slv_Slv = 407
-    Ieee_Std_Logic_Signed_Add_Slv_Int = 408
-    Ieee_Std_Logic_Signed_Add_Int_Slv = 409
-    Ieee_Std_Logic_Signed_Add_Slv_Sl = 410
-    Ieee_Std_Logic_Signed_Add_Sl_Slv = 411
-    Ieee_Std_Logic_Signed_Sub_Slv_Slv = 412
-    Ieee_Std_Logic_Signed_Sub_Slv_Int = 413
-    Ieee_Std_Logic_Signed_Sub_Int_Slv = 414
-    Ieee_Std_Logic_Signed_Sub_Slv_Sl = 415
-    Ieee_Std_Logic_Signed_Sub_Sl_Slv = 416
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 417
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 418
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 419
-    Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 420
-    Ieee_Std_Logic_Arith_Conv_Integer_Int = 421
-    Ieee_Std_Logic_Arith_Conv_Integer_Uns = 422
-    Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 423
-    Ieee_Std_Logic_Arith_Conv_Integer_Log = 424
-    Ieee_Std_Logic_Arith_Conv_Vector_Int = 425
-    Ieee_Std_Logic_Arith_Conv_Vector_Uns = 426
-    Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 427
-    Ieee_Std_Logic_Arith_Conv_Vector_Log = 428
-    Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 429
-    Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 430
-    Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 431
-    Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 432
-    Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 433
-    Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 434
-    Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 435
-    Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 436
-    Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 437
-    Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 438
-    Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 439
-    Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 440
-    Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 441
-    Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 442
-    Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 443
-    Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 444
-    Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 445
-    Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 446
-    Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 447
-    Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 448
-    Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 449
-    Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 450
-    Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 451
-    Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 452
-    Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 453
-    Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 454
-    Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 455
-    Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 456
-    Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 457
-    Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 458
-    Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 459
-    Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 460
+    Ieee_Std_Logic_Unsigned_Sub_Slv_Log = 386
+    Ieee_Std_Logic_Unsigned_Sub_Log_Slv = 387
+    Ieee_Std_Logic_Unsigned_Mul_Slv_Slv = 388
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 389
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 390
+    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 391
+    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 392
+    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 393
+    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 394
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 395
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 396
+    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 397
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 398
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 399
+    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 400
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 401
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 402
+    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 403
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 404
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 405
+    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 406
+    Ieee_Std_Logic_Unsigned_Conv_Integer = 407
+    Ieee_Std_Logic_Signed_Add_Slv_Slv = 408
+    Ieee_Std_Logic_Signed_Add_Slv_Int = 409
+    Ieee_Std_Logic_Signed_Add_Int_Slv = 410
+    Ieee_Std_Logic_Signed_Add_Slv_Log = 411
+    Ieee_Std_Logic_Signed_Add_Log_Slv = 412
+    Ieee_Std_Logic_Signed_Sub_Slv_Slv = 413
+    Ieee_Std_Logic_Signed_Sub_Slv_Int = 414
+    Ieee_Std_Logic_Signed_Sub_Int_Slv = 415
+    Ieee_Std_Logic_Signed_Sub_Slv_Log = 416
+    Ieee_Std_Logic_Signed_Sub_Log_Slv = 417
+    Ieee_Std_Logic_Signed_Mul_Slv_Slv = 418
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 419
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 420
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 421
+    Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 422
+    Ieee_Std_Logic_Arith_Conv_Integer_Int = 423
+    Ieee_Std_Logic_Arith_Conv_Integer_Uns = 424
+    Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 425
+    Ieee_Std_Logic_Arith_Conv_Integer_Log = 426
+    Ieee_Std_Logic_Arith_Conv_Vector_Int = 427
+    Ieee_Std_Logic_Arith_Conv_Vector_Uns = 428
+    Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 429
+    Ieee_Std_Logic_Arith_Conv_Vector_Log = 430
+    Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 431
+    Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 432
+    Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 433
+    Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 434
+    Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 435
+    Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 436
+    Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 437
+    Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 438
+    Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 439
+    Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 440
+    Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 441
+    Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 442
+    Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 443
+    Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 444
+    Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 445
+    Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 446
+    Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 447
+    Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 448
+    Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 449
+    Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 450
+    Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 451
+    Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 452
+    Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 453
+    Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 454
+    Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 455
+    Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 456
+    Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 457
+    Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 458
+    Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 459
+    Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 460
+    Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 461
+    Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 462
 
 Get_Kind = libghdl.vhdl__nodes__get_kind
 Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 2fa4fad9c..e3fd0c714 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -398,12 +398,20 @@ package body Synth.Oper is
                                 return Value_Acc
       is
          W : constant Width := Width'Max (Left.Typ.W, Right.Typ.W);
+         El_Typ : Type_Acc;
          Rtype : Type_Acc;
          L1, R1 : Net;
          N : Net;
       begin
          if Is_Res_Vec then
-            Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
+            if Left.Typ.Kind = Type_Vector then
+               El_Typ := Left.Typ.Vec_El;
+            elsif Right.Typ.Kind = Type_Vector then
+               El_Typ := Right.Typ.Vec_El;
+            else
+               raise Internal_Error;
+            end if;
+            Rtype := Create_Vec_Type_By_Length (W, El_Typ);
          else
             Rtype := Left.Typ;
          end if;
@@ -809,7 +817,7 @@ package body Synth.Oper is
             return Synth_Dyadic_Nat_Uns (Id_Add);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
            | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
-           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv
            | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv =>
             --  "+" (Unsigned, Unsigned)
@@ -826,7 +834,8 @@ package body Synth.Oper is
            | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn
            | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn
            | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn
-           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv =>
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv =>
             --  "+" (Signed, Signed)
             return Synth_Dyadic_Sgn (Id_Add, True);
 
@@ -836,7 +845,8 @@ package body Synth.Oper is
             return Synth_Dyadic_Uns_Nat (Id_Sub);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv
-           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl =>
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log =>
             --  "-" (Unsigned, Unsigned)
             return Synth_Dyadic_Uns (Id_Sub, True);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int
@@ -854,7 +864,9 @@ package body Synth.Oper is
 
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn
            | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn
-           | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv =>
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv =>
+            --  "*" (Signed, Signed)
             declare
                W : constant Width := Left.Typ.W + Right.Typ.W;
                L, R : Net;
@@ -899,7 +911,9 @@ package body Synth.Oper is
             end;
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns
            | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns
-           | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv =>
+           | Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv =>
+            --  "*" (unsigned, unsigned)
             declare
                W : constant Width := Left.Typ.W + Right.Typ.W;
                Rtype : Type_Acc;
@@ -1125,7 +1139,8 @@ package body Synth.Oper is
             --  ">=" (Natural, Unsigned) [resize]
             return Synth_Compare_Nat_Uns (Id_Uge, Expr_Typ);
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Uns_Nat
-           | Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Uns_Nat =>
+           | Iir_Predefined_Ieee_Numeric_Std_Match_Ge_Uns_Nat
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Ge_Slv_Int =>
             --  ">=" (Unsigned, Natural)
             return Synth_Compare_Uns_Nat (Id_Uge, Expr_Typ);
          when Iir_Predefined_Ieee_Numeric_Std_Ge_Sgn_Sgn
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
index 69893b954..0fcc45911 100644
--- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb
@@ -21,9 +21,9 @@ with Std_Names; use Std_Names;
 with Vhdl.Ieee.Std_Logic_1164;
 
 package body Vhdl.Ieee.Std_Logic_Unsigned is
-   type Arg_Kind is (Arg_Slv, Arg_Int, Arg_Sl);
+   type Arg_Kind is (Arg_Slv, Arg_Int, Arg_Log);
    type Args_Kind is (Arg_Slv_Slv, Arg_Slv_Int, Arg_Int_Slv,
-                      Arg_Slv_Sl, Arg_Sl_Slv);
+                      Arg_Slv_Log, Arg_Log_Slv);
 
    type Binary_Pattern_Type is array (Args_Kind) of Iir_Predefined_Functions;
 
@@ -70,29 +70,29 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is
      (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv,
       Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int,
       Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv,
-      Arg_Slv_Sl  => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl,
-      Arg_Sl_Slv  => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv);
+      Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log,
+      Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv);
 
    Sub_Uns_Patterns : constant Binary_Pattern_Type :=
      (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv,
       Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int,
       Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv,
-      Arg_Slv_Sl  => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl,
-      Arg_Sl_Slv  => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv);
+      Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log,
+      Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv);
 
    Add_Sgn_Patterns : constant Binary_Pattern_Type :=
      (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv,
       Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int,
       Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv,
-      Arg_Slv_Sl  => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl,
-      Arg_Sl_Slv  => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv);
+      Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log,
+      Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv);
 
    Sub_Sgn_Patterns : constant Binary_Pattern_Type :=
      (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv,
       Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int,
       Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv,
-      Arg_Slv_Sl  => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl,
-      Arg_Sl_Slv  => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv);
+      Arg_Slv_Log => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log,
+      Arg_Log_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv);
 
    Error : exception;
 
@@ -106,7 +106,7 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is
          if Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then
             Kind := Arg_Int;
          elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type then
-            Kind := Arg_Sl;
+            Kind := Arg_Log;
          elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then
             Kind := Arg_Slv;
          else
@@ -129,19 +129,19 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is
             when Arg_Slv =>
                case Arg2_Kind is
                   when Arg_Slv => Kind := Arg_Slv_Slv;
-                  when Arg_Sl => Kind := Arg_Slv_Sl;
+                  when Arg_Log => Kind := Arg_Slv_Log;
                   when Arg_Int => Kind := Arg_Slv_Int;
                end case;
             when Arg_Int =>
                case Arg2_Kind is
                   when Arg_Slv => Kind := Arg_Int_Slv;
-                  when Arg_Sl
+                  when Arg_Log
                     | Arg_Int => raise Error;
                end case;
-            when Arg_Sl =>
+            when Arg_Log =>
                case Arg2_Kind is
-                  when Arg_Slv => Kind := Arg_Sl_Slv;
-                  when Arg_Sl
+                  when Arg_Slv => Kind := Arg_Log_Slv;
+                  when Arg_Log
                     | Arg_Int => raise Error;
                end case;
          end case;
@@ -194,6 +194,19 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is
                   Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns);
                when Name_Op_Minus =>
                   Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns);
+               when Name_Op_Mul =>
+                  case Sign is
+                     when Pkg_Unsigned =>
+                        pragma Assert (Arg1_Kind = Arg_Slv);
+                        pragma Assert (Arg2_Kind = Arg_Slv);
+                        Res :=
+                          Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv;
+                     when Pkg_Signed =>
+                        pragma Assert (Arg1_Kind = Arg_Slv);
+                        pragma Assert (Arg2_Kind = Arg_Slv);
+                        Res :=
+                          Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv;
+                  end case;
                when others =>
                   null;
             end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 56c231301..8be86f9dd 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5689,14 +5689,16 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv,
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int,
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv,
-      Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl,
-      Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log,
+      Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv,
 
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv,
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int,
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv,
-      Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl,
-      Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log,
+      Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv,
+
+      Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv,
 
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv,
       Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int,
@@ -5728,14 +5730,16 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv,
       Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int,
       Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv,
-      Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl,
-      Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log,
+      Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv,
 
       Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv,
       Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int,
       Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv,
-      Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl,
-      Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv,
+      Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log,
+      Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv,
+
+      Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv,
 
       --  std_logic_arith (synopsys extention).
       Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int,