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| author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-08-07 04:20:14 +0200 |
|---|---|---|
| committer | tgingold <tgingold@users.noreply.github.com> | 2019-08-07 04:20:14 +0200 |
| commit | 0331772c3ef05bad40b748542939ccafab2a9c68 (patch) | |
| tree | ca0dd705571b8a031c02b6934d9e9fe85151b042 /src/vhdl/vhdl-nodes.adb | |
| parent | ce416ec62d20f1a592835efe5cbe49856d7085a2 (diff) | |
| download | ghdl-0331772c3ef05bad40b748542939ccafab2a9c68.tar.gz ghdl-0331772c3ef05bad40b748542939ccafab2a9c68.tar.bz2 ghdl-0331772c3ef05bad40b748542939ccafab2a9c68.zip | |
Add support for PSL assumptions, used in formal verification (#880)
* vhdl: make the parser understand PSL assume
* assume does not actually have report according to the spec. Just a property.
* add SPL assume to semantic analysis
* canonicalise PSL assume
* add assume to annotations
* add PSL assume to simulation code
* statement -> directive
* add assume to translation files
* update ticked24 testcase
* correctly parse assume
* add assume testcase
* refactor chunk of duplicated code
Diffstat (limited to 'src/vhdl/vhdl-nodes.adb')
| -rw-r--r-- | src/vhdl/vhdl-nodes.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index dfb9629af..780f13b5b 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1235,7 +1235,8 @@ package body Vhdl.Nodes is | Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment - | Iir_Kind_Psl_Assert_Statement + | Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement |