From 0331772c3ef05bad40b748542939ccafab2a9c68 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 7 Aug 2019 04:20:14 +0200 Subject: Add support for PSL assumptions, used in formal verification (#880) * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code --- src/vhdl/vhdl-nodes.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/vhdl/vhdl-nodes.adb') diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index dfb9629af..780f13b5b 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1235,7 +1235,8 @@ package body Vhdl.Nodes is | Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment - | Iir_Kind_Psl_Assert_Statement + | Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Block_Statement -- cgit v1.2.3