From 67f926fc1323c375d14fee36a092e39a92d505dd Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 27 May 2020 08:00:42 +0200 Subject: synth: handle reduction operators. Fix #1342 --- src/vhdl/vhdl-ieee-std_logic_1164.adb | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'src/vhdl/vhdl-ieee-std_logic_1164.adb') diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 58fe96229..bb4b12bce 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -375,11 +375,17 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Not => Predefined := Iir_Predefined_Ieee_1164_Vector_Not; when Name_And => - Predefined := - Iir_Predefined_Ieee_1164_Vector_And_Reduce; + Predefined := Iir_Predefined_Ieee_1164_And_Suv; + when Name_Nand => + Predefined := Iir_Predefined_Ieee_1164_Nand_Suv; when Name_Or => - Predefined := - Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + Predefined := Iir_Predefined_Ieee_1164_Or_Suv; + when Name_Nor => + Predefined := Iir_Predefined_Ieee_1164_Nor_Suv; + when Name_Xor => + Predefined := Iir_Predefined_Ieee_1164_Xor_Suv; + when Name_Xnor => + Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => Predefined := Iir_Predefined_Ieee_1164_Scalar_Is_X; -- cgit v1.2.3