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| author | Tristan Gingold <tgingold@free.fr> | 2017-11-08 05:45:55 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-11-08 05:45:55 +0100 |
| commit | 9e01b1290d44a275160a0d87454e35918fe0d2e5 (patch) | |
| tree | 162a7dbc77d34b87fd8d09105b0c5e26ae4cf70b /src/vhdl/translate/trans-chap5.adb | |
| parent | e663f3eaa705b80acdb7c97f52ac50b4beb76b7d (diff) | |
| download | ghdl-9e01b1290d44a275160a0d87454e35918fe0d2e5.tar.gz ghdl-9e01b1290d44a275160a0d87454e35918fe0d2e5.tar.bz2 ghdl-9e01b1290d44a275160a0d87454e35918fe0d2e5.zip | |
Use flist for disconnection specification and component specification.
Diffstat (limited to 'src/vhdl/translate/trans-chap5.adb')
| -rw-r--r-- | src/vhdl/translate/trans-chap5.adb | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index ac054f394..e989b8075 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -160,15 +160,14 @@ package body Trans.Chap5 is (Spec : Iir_Disconnection_Specification) is Val : O_Dnode; - List : constant Iir_List := Get_Signal_List (Spec); + List : constant Iir_Flist := Get_Signal_List (Spec); El : Iir; begin Val := Create_Temp_Init (Std_Time_Otype, Chap7.Translate_Expression (Get_Expression (Spec))); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Gen_Elab_Disconnect (Chap6.Translate_Name (El, Mode_Signal), Get_Type (El), Val); end loop; |