From 9e01b1290d44a275160a0d87454e35918fe0d2e5 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 8 Nov 2017 05:45:55 +0100 Subject: Use flist for disconnection specification and component specification. --- src/vhdl/translate/trans-chap5.adb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/vhdl/translate/trans-chap5.adb') diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index ac054f394..e989b8075 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -160,15 +160,14 @@ package body Trans.Chap5 is (Spec : Iir_Disconnection_Specification) is Val : O_Dnode; - List : constant Iir_List := Get_Signal_List (Spec); + List : constant Iir_Flist := Get_Signal_List (Spec); El : Iir; begin Val := Create_Temp_Init (Std_Time_Otype, Chap7.Translate_Expression (Get_Expression (Spec))); - for I in Natural loop + for I in Flist_First .. Flist_Last (List) loop El := Get_Nth_Element (List, I); - exit when El = Null_Iir; Gen_Elab_Disconnect (Chap6.Translate_Name (El, Mode_Signal), Get_Type (El), Val); end loop; -- cgit v1.2.3