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authorTristan Gingold <tgingold@free.fr>2016-06-30 06:15:30 +0200
committerTristan Gingold <tgingold@free.fr>2016-07-03 14:16:16 +0200
commitf100e7c33b3064d92a46ef09936aebd899203d8e (patch)
treec25d8afd083fadd7572efa246094c5901cf9e5e4 /src/vhdl/translate/trans-chap12.adb
parent906d23d23591b2040b3554e7aa39ecfe0c9a1e1b (diff)
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Enable vest recursive instantiation test.
Diffstat (limited to 'src/vhdl/translate/trans-chap12.adb')
-rw-r--r--src/vhdl/translate/trans-chap12.adb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index a5f2e9cfd..25b73fa71 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -658,6 +658,10 @@ package body Trans.Chap12 is
Rtis.Generate_Library (Libraries.Std_Library, True);
Translate_Standard (Whole);
+ -- Std.Standard has no body and is always in the closure. Exclude it
+ -- from the stub and filelist generation.
+ Set_Elab_Flag (Std_Standard_Unit, True);
+
-- Translate all configurations needed.
-- Also, set the ELAB_FLAG on package with body.
for I in Design_Units.First .. Design_Units.Last loop