diff options
| -rw-r--r-- | src/vhdl/configuration.adb | 11 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap12.adb | 4 | ||||
| -rw-r--r-- | src/vhdl/translate/trans-chap5.adb | 16 | ||||
| -rw-r--r-- | testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp | 10 |
4 files changed, 28 insertions, 13 deletions
diff --git a/src/vhdl/configuration.adb b/src/vhdl/configuration.adb index e4b862f3b..8c442dd76 100644 --- a/src/vhdl/configuration.adb +++ b/src/vhdl/configuration.adb @@ -52,9 +52,14 @@ package body Configuration is -- If already in the table, then nothing to do. if Get_Configuration_Mark_Flag (Unit) then - if not Get_Configuration_Done_Flag (Unit) then - raise Internal_Error; - end if; + -- There might be some direct recursions: + -- * the default configuration might be implicitly referenced by + -- a direct entity instantiation + -- * a configuration may be referenced by itself for a recursive + -- instantiation + pragma Assert (Get_Configuration_Done_Flag (Unit) + or else (Get_Kind (Get_Library_Unit (Unit)) + = Iir_Kind_Configuration_Declaration)); return; end if; Set_Configuration_Mark_Flag (Unit, True); diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb index a5f2e9cfd..25b73fa71 100644 --- a/src/vhdl/translate/trans-chap12.adb +++ b/src/vhdl/translate/trans-chap12.adb @@ -658,6 +658,10 @@ package body Trans.Chap12 is Rtis.Generate_Library (Libraries.Std_Library, True); Translate_Standard (Whole); + -- Std.Standard has no body and is always in the closure. Exclude it + -- from the stub and filelist generation. + Set_Elab_Flag (Std_Standard_Unit, True); + -- Translate all configurations needed. -- Also, set the ELAB_FLAG on package with body. for I in Design_Units.First .. Design_Units.Last loop diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb index c115b84b4..7bdb84385 100644 --- a/src/vhdl/translate/trans-chap5.adb +++ b/src/vhdl/translate/trans-chap5.adb @@ -36,7 +36,10 @@ package body Trans.Chap5 is Scope => Scope_Ptr.all); end Save_Map_Env; - procedure Set_Map_Env (Env : Map_Env) is + procedure Set_Map_Env (Env : Map_Env) + is + -- Avoid potential compiler bug with discriminant check. + pragma Suppress (Discriminant_Check); begin Env.Scope_Ptr.all := Env.Scope; end Set_Map_Env; @@ -421,9 +424,10 @@ package body Trans.Chap5 is end if; else - Set_Map_Env (Actual_Env); - Actual_En := Chap7.Translate_Expression (Actual, Formal_Type); + -- Association by value. The formal cannot be referenced in the + -- actual. Set_Map_Env (Formal_Env); + Actual_En := Chap7.Translate_Expression (Actual, Formal_Type); Actual_Sig := E2M (Actual_En, Get_Info (Formal_Type), Mode_Value); Chap6.Translate_Signal_Name (Formal, Formal_Sig, Formal_Val); Mode := Connect_Value; @@ -449,12 +453,12 @@ package body Trans.Chap5 is Chap4.Elab_In_Conversion (Assoc, Actual_Sig); Set_Map_Env (Formal_Env); Formal_Sig := Chap6.Translate_Name (Formal, Mode_Signal); - Set_Map_Env (Actual_Env); Data := (Actual_Sig => Actual_Sig, Actual_Type => Formal_Type, Mode => Connect_Effective, By_Copy => False); Connect (Formal_Sig, Formal_Type, Data); + Set_Map_Env (Actual_Env); end if; if Get_Out_Conversion (Assoc) /= Null_Iir then -- flow: FORMAL to ACTUAL @@ -639,7 +643,9 @@ package body Trans.Chap5 is begin Set_Map_Env (Formal_Env); -- Set bounds of unconstrained ports. - if Fbt_Info.Type_Mode = Type_Mode_Fat_Array then + if Get_Whole_Association_Flag (Assoc) + and then Fbt_Info.Type_Mode = Type_Mode_Fat_Array + then Open_Temp; Elab_Unconstrained_Port_Bounds (Formal, Assoc); Close_Temp; diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp index 1f1056cc8..b2fd0bf72 100644 --- a/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp +++ b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp @@ -142,7 +142,7 @@ build_compliant_test ch_04_ch_04_04.vhd build_compliant_test ch_04_ch_04_05.vhd build_compliant_test ch_04_ch_04_06.vhd build_compliant_test ch_04_ch_04_07.vhd -#build_compliant_test ch_04_ch_04_08.vhd # error detected during analysis +#build_compliant_test ch_04_ch_04_08.vhd # contains errors (invalid ranges) build_compliant_test ch_04_ch_04_10.vhd build_compliant_test ch_04_fg_04_01.vhd @@ -252,7 +252,7 @@ build_compliant_test ch_05_fg_05_17.vhd build_compliant_test ch_05_fg_05_18.vhd build_compliant_test ch_05_fg_05_19.vhd build_compliant_test ch_05_fg_05_20.vhd -#build_compliant_test ch_05_fg_05_21.vhd # bad expression for selected sig asgn +#build_compliant_test ch_05_fg_05_21.vhd # error: non-static tyoe mark in selected sig asgn build_compliant_test ch_05_fg_05_23.vhd build_compliant_test ch_05_fg_05_25.vhd build_compliant_test ch_05_fg_05_28.vhd @@ -368,7 +368,7 @@ build_compliant_test ch_09_ch_09_01.vhd build_compliant_test ch_09_ch_09_02.vhd build_compliant_test ch_09_ch_09_03.vhd build_compliant_test ch_09_ch_09_04.vhd -#build_compliant_test ch_09_fg_09_01.vhd # non-object alias denotes an object +build_compliant_test ch_09_fg_09_01.vhd build_compliant_test ch_09_fg_09_02.vhd build_compliant_test ch_09_fg_09_03.vhd build_compliant_test ch_09_fg_09_04.vhd @@ -433,7 +433,7 @@ build_compliant_test ch_13_fg_13_01.vhd LIBRARY=star_lib build_compliant_test ch_13_fg_13_02.vhd build_compliant_test ch_13_fg_13_03.vhd build_compliant_test ch_13_fg_13_04.vhd -#build_compliant_test ch_13_fg_13_05.vhd # depend +#build_compliant_test ch_13_fg_13_05.vhd # depend (no star_lib) build_compliant_test ch_13_fg_13_06.vhd #build_compliant_test ch_13_fg_13_07.vhd # depend #build_compliant_test ch_13_fg_13_08.vhd # depend @@ -491,7 +491,7 @@ build_compliant_test ch_14_fg_14_04.vhd LIBRARY=chip_lib #build_compliant_test ch_14_fg_14_05.vhd # array staticness #build_compliant_test ch_14_fg_14_05.vhd LIBRARY=cell_lib build_compliant_test ch_14_fg_14_06.vhd -#build_compliant_test ch_14_fg_14_08.vhd # recursive instantiation +build_compliant_test ch_14_fg_14_08.vhd # recursive instantiation build_compliant_test ch_14_fg_14_09.vhd build_compliant_test ch_14_fg_14_10.vhd build_compliant_test ch_14_fg_14_11.vhd |