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authorTristan Gingold <tgingold@free.fr>2017-12-11 18:41:42 +0100
committerTristan Gingold <tgingold@free.fr>2017-12-11 18:41:42 +0100
commitce3659abec1037f8dc4ad62eecdaba08884ce348 (patch)
tree3189774f85512fcb16523ef890b466b77ab33a88 /src/vhdl/simulate/simul-execution.adb
parent1451879337efac06519bbcb080729172d03d4a58 (diff)
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simul: Check range of the result of concat operator.
Diffstat (limited to 'src/vhdl/simulate/simul-execution.adb')
-rw-r--r--src/vhdl/simulate/simul-execution.adb21
1 files changed, 18 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index b953d6d51..2eb890c54 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -657,6 +657,10 @@ package body Simul.Execution is
Eval_Right;
declare
+ -- Type of the index.
+ Idx_Type : constant Iir :=
+ Get_Nth_Element (Get_Index_Subtype_List (Res_Type), 0);
+
-- Array length of the result.
Len: Iir_Index32;
@@ -714,10 +718,10 @@ package body Simul.Execution is
-- Create the array result.
Result := Create_Array_Value (Len, 1);
Result.Bounds.D (1) := Create_Bounds_From_Length
- (Block,
- Get_Nth_Element (Get_Index_Subtype_List (Res_Type), 0),
- Len);
+ (Block, Idx_Type, Len);
end if;
+ Check_Range_Constraints
+ (Block, Result.Bounds.D (1), Idx_Type, Expr);
-- Fill the result: left.
case Func is
@@ -3868,6 +3872,17 @@ package body Simul.Execution is
Value := Ref_Value;
end Implicit_Array_Conversion;
+ procedure Check_Range_Constraints (Instance : Block_Instance_Acc;
+ Rng : Iir_Value_Literal_Acc;
+ Rng_Type : Iir;
+ Loc : Iir) is
+ begin
+ if not Is_Null_Range (Rng) then
+ Check_Constraints (Instance, Rng.Left, Get_Type (Rng_Type), Loc);
+ Check_Constraints (Instance, Rng.Right, Get_Type (Rng_Type), Loc);
+ end if;
+ end Check_Range_Constraints;
+
procedure Check_Array_Constraints
(Instance: Block_Instance_Acc;
Value: Iir_Value_Literal_Acc;