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author | Tristan Gingold <tgingold@free.fr> | 2019-05-30 14:28:12 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-30 14:28:12 +0200 |
commit | ad46e4bed268a9c4faefb503deec7dc5603a9be2 (patch) | |
tree | d7557d67b2b4539426a3ea008e9655233214604f /src/vhdl/simulate/simul-debugger.adb | |
parent | 5ca1572dbef924b659e7ecc912686d3941b5ae30 (diff) | |
download | ghdl-ad46e4bed268a9c4faefb503deec7dc5603a9be2.tar.gz ghdl-ad46e4bed268a9c4faefb503deec7dc5603a9be2.tar.bz2 ghdl-ad46e4bed268a9c4faefb503deec7dc5603a9be2.zip |
vhdl: differenciate block and line comments.
Diffstat (limited to 'src/vhdl/simulate/simul-debugger.adb')
-rw-r--r-- | src/vhdl/simulate/simul-debugger.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb index 652828b19..93f926048 100644 --- a/src/vhdl/simulate/simul-debugger.adb +++ b/src/vhdl/simulate/simul-debugger.adb @@ -37,7 +37,7 @@ with Simul.Execution; use Simul.Execution; with Vhdl.Utils; use Vhdl.Utils; with Errorout; use Errorout; with Vhdl.Errors; use Vhdl.Errors; -with Vhdl.Disp_Vhdl; +with Vhdl.Prints; with Vhdl.Nodes_Walk; use Vhdl.Nodes_Walk; with Areapools; use Areapools; with Grt.Types; use Grt.Types; @@ -1521,7 +1521,7 @@ package body Simul.Debugger is Put ('.'); Put (Name_Table.Image (Get_Identifier (E.Stmt))); New_Line; - Vhdl.Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); + Vhdl.Prints.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt)); Put (" 01234567890123456789012345678901234567890123456789"); for I in E.States'Range loop if I mod 50 = 0 then @@ -1925,7 +1925,7 @@ package body Simul.Debugger is return; end if; - Vhdl.Disp_Vhdl.Disp_Expression (Expr); + Vhdl.Prints.Disp_Expression (Expr); New_Line; Annotate_Expand_Table; |