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authorTristan Gingold <tgingold@free.fr>2019-05-30 14:28:12 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-30 14:28:12 +0200
commitad46e4bed268a9c4faefb503deec7dc5603a9be2 (patch)
treed7557d67b2b4539426a3ea008e9655233214604f /src/vhdl/simulate
parent5ca1572dbef924b659e7ecc912686d3941b5ae30 (diff)
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vhdl: differenciate block and line comments.
Diffstat (limited to 'src/vhdl/simulate')
-rw-r--r--src/vhdl/simulate/simul-debugger-ams.adb4
-rw-r--r--src/vhdl/simulate/simul-debugger.adb6
2 files changed, 5 insertions, 5 deletions
diff --git a/src/vhdl/simulate/simul-debugger-ams.adb b/src/vhdl/simulate/simul-debugger-ams.adb
index 828e5bdbc..2c5098839 100644
--- a/src/vhdl/simulate/simul-debugger-ams.adb
+++ b/src/vhdl/simulate/simul-debugger-ams.adb
@@ -18,7 +18,7 @@
with Simple_IO; use Simple_IO;
with Vhdl.Utils; use Vhdl.Utils;
-with Vhdl.Disp_Vhdl;
+with Vhdl.Prints;
package body Simul.Debugger.AMS is
procedure Disp_Quantity_Name (Quantity : Quantity_Index_Type)
@@ -46,7 +46,7 @@ package body Simul.Debugger.AMS is
when Op_Quantity =>
Disp_Quantity_Name (Term.Quantity);
when Op_Vhdl_Expr =>
- Vhdl.Disp_Vhdl.Disp_Expression (Term.Vhdl_Expr);
+ Vhdl.Prints.Disp_Expression (Term.Vhdl_Expr);
end case;
end Disp_Term;
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 652828b19..93f926048 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -37,7 +37,7 @@ with Simul.Execution; use Simul.Execution;
with Vhdl.Utils; use Vhdl.Utils;
with Errorout; use Errorout;
with Vhdl.Errors; use Vhdl.Errors;
-with Vhdl.Disp_Vhdl;
+with Vhdl.Prints;
with Vhdl.Nodes_Walk; use Vhdl.Nodes_Walk;
with Areapools; use Areapools;
with Grt.Types; use Grt.Types;
@@ -1521,7 +1521,7 @@ package body Simul.Debugger is
Put ('.');
Put (Name_Table.Image (Get_Identifier (E.Stmt)));
New_Line;
- Vhdl.Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt));
+ Vhdl.Prints.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt));
Put (" 01234567890123456789012345678901234567890123456789");
for I in E.States'Range loop
if I mod 50 = 0 then
@@ -1925,7 +1925,7 @@ package body Simul.Debugger is
return;
end if;
- Vhdl.Disp_Vhdl.Disp_Expression (Expr);
+ Vhdl.Prints.Disp_Expression (Expr);
New_Line;
Annotate_Expand_Table;