diff options
| -rw-r--r-- | python/libghdl/thin/std_names.py | 4 | ||||
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 18 | ||||
| -rw-r--r-- | src/std_names.adb | 2 | ||||
| -rw-r--r-- | src/std_names.ads | 4 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 52 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.ads | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 13 | ||||
| -rw-r--r-- | src/vhdl/vhdl-post_sems.adb | 6 |
9 files changed, 85 insertions, 24 deletions
diff --git a/python/libghdl/thin/std_names.py b/python/libghdl/thin/std_names.py index c2ddef117..e9b7308b7 100644 --- a/python/libghdl/thin/std_names.py +++ b/python/libghdl/thin/std_names.py @@ -583,8 +583,8 @@ class Name: Unresolved_Signed = 797 Std_Logic_Arith = 798 Std_Logic_Signed = 799 - Std_Logic_Textio = 800 - Std_Logic_Unsigned = 801 + Std_Logic_Unsigned = 800 + Std_Logic_Textio = 801 To_Integer = 802 To_Unsigned = 803 To_Signed = 804 diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index d684700a6..b77434aa7 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1199,10 +1199,20 @@ class Iir_Predefined: Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 320 Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 321 Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 322 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 323 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 324 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 325 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 326 + Ieee_Std_Logic_Signed_Add_Slv_Slv = 323 + Ieee_Std_Logic_Signed_Add_Slv_Int = 324 + Ieee_Std_Logic_Signed_Add_Int_Slv = 325 + Ieee_Std_Logic_Signed_Add_Slv_Sl = 326 + Ieee_Std_Logic_Signed_Add_Sl_Slv = 327 + Ieee_Std_Logic_Signed_Sub_Slv_Slv = 328 + Ieee_Std_Logic_Signed_Sub_Slv_Int = 329 + Ieee_Std_Logic_Signed_Sub_Int_Slv = 330 + Ieee_Std_Logic_Signed_Sub_Slv_Sl = 331 + Ieee_Std_Logic_Signed_Sub_Sl_Slv = 332 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 333 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 334 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 335 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 336 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/std_names.adb b/src/std_names.adb index f1042a7d9..a19c9c6c0 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -635,8 +635,8 @@ package body Std_Names is Def ("unresolved_signed", Name_Unresolved_Signed); Def ("std_logic_arith", Name_Std_Logic_Arith); Def ("std_logic_signed", Name_Std_Logic_Signed); - Def ("std_logic_textio", Name_Std_Logic_Textio); Def ("std_logic_unsigned", Name_Std_Logic_Unsigned); + Def ("std_logic_textio", Name_Std_Logic_Textio); Def ("to_integer", Name_To_Integer); Def ("to_unsigned", Name_To_Unsigned); Def ("to_signed", Name_To_Signed); diff --git a/src/std_names.ads b/src/std_names.ads index 81a878ee4..db3e82414 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -716,8 +716,8 @@ package Std_Names is Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 014; Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 015; Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 016; - Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 017; - Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 018; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 017; + Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 018; Name_To_Integer : constant Name_Id := Name_First_Ieee + 019; Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020; Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 62bc1a51e..6754193aa 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -514,7 +514,8 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns => -- "-" (Unsigned, Unsigned) return Synth_Dyadic_Uns (Id_Sub, True); - when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int => + when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int + | Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int => -- "-" (Signed, Integer) return Synth_Dyadic_Sgn_Int (Id_Sub); when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn => diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 7e2b86c02..9e2bb5269 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -27,6 +27,9 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is type Binary_Pattern_Type is array (Args_Kind) of Iir_Predefined_Functions; + None_Patterns : constant Binary_Pattern_Type := + (others => Iir_Predefined_None); + Eq_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, @@ -51,23 +54,38 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, others => Iir_Predefined_None); - Add_Patterns : constant Binary_Pattern_Type := + Add_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); - Sub_Patterns : constant Binary_Pattern_Type := + Sub_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv); + Add_Sgn_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv); + + Sub_Sgn_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv); + Error : exception; - procedure Extract_Declarations (Pkg : Iir_Package_Declaration) + procedure Extract_Declarations + (Pkg : Iir_Package_Declaration; Sign : Sign_Kind) is procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind) is @@ -89,7 +107,9 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg1, Arg2 : Iir; Arg1_Kind, Arg2_Kind : Arg_Kind; - procedure Handle_Binary (Pats : Binary_Pattern_Type) + function Handle_Binary (Unsigned_Pats : Binary_Pattern_Type; + Signed_Pats : Binary_Pattern_Type) + return Iir_Predefined_Functions is Kind : Args_Kind; begin @@ -114,8 +134,15 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is end case; end case; - Set_Implicit_Definition (Decl, Pats (Kind)); + case Sign is + when Pkg_Unsigned => + return Unsigned_Pats (Kind); + when Pkg_Signed => + return Signed_Pats (Kind); + end case; end Handle_Binary; + + Res : Iir_Predefined_Functions; begin Decl := Get_Declaration_Chain (Pkg); @@ -130,6 +157,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is raise Error; end if; + Res := Iir_Predefined_None; + Classify_Arg (Arg1, Arg1_Kind); Arg2 := Get_Chain (Arg1); if Is_Valid (Arg2) then @@ -138,17 +167,17 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => - Handle_Binary (Eq_Patterns); + Res := Handle_Binary (Eq_Patterns, None_Patterns); when Name_Op_Inequality => - Handle_Binary (Ne_Patterns); + Res := Handle_Binary (Ne_Patterns, None_Patterns); when Name_Op_Less => - Handle_Binary (Lt_Patterns); + Res := Handle_Binary (Lt_Patterns, None_Patterns); when Name_Op_Less_Equal => - Handle_Binary (Le_Patterns); + Res := Handle_Binary (Le_Patterns, None_Patterns); when Name_Op_Plus => - Handle_Binary (Add_Patterns); + Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); when Name_Op_Minus => - Handle_Binary (Sub_Patterns); + Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns); when others => null; end case; @@ -159,6 +188,7 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is null; end case; end if; + Set_Implicit_Definition (Decl, Res); Decl := Get_Chain (Decl); end loop; end Extract_Declarations; diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.ads b/src/vhdl/vhdl-ieee-std_logic_unsigned.ads index 8ad54fd05..1e8cca5be 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.ads +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.ads @@ -1,4 +1,4 @@ --- Nodes recognizer for ieee.std_logic_unsigned +-- Nodes recognizer for ieee.std_logic_unsigned and ieee.std_logic_signed. -- Copyright (C) 2019 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under @@ -17,6 +17,9 @@ -- 02111-1307, USA. package Vhdl.Ieee.Std_Logic_Unsigned is + type Sign_Kind is (Pkg_Unsigned, Pkg_Signed); + -- Extract declarations from PKG . - procedure Extract_Declarations (Pkg : Iir_Package_Declaration); + procedure Extract_Declarations + (Pkg : Iir_Package_Declaration; Sign : Sign_Kind); end Vhdl.Ieee.Std_Logic_Unsigned; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index f903a4c4d..44d25880d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5093,6 +5093,19 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + -- Std_Logic_Signed (synopsys extension). + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv, + -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb index e5805ea59..8924a1d45 100644 --- a/src/vhdl/vhdl-post_sems.adb +++ b/src/vhdl/vhdl-post_sems.adb @@ -63,7 +63,11 @@ package body Vhdl.Post_Sems is when Name_Math_Real => Vhdl.Ieee.Math_Real.Extract_Declarations (Lib_Unit); when Name_Std_Logic_Unsigned => - Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations (Lib_Unit); + Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations + (Lib_Unit, Vhdl.Ieee.Std_Logic_Unsigned.Pkg_Unsigned); + when Name_Std_Logic_Signed => + Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations + (Lib_Unit, Vhdl.Ieee.Std_Logic_Unsigned.Pkg_Signed); when Name_Std_Logic_Arith => Vhdl.Ieee.Std_Logic_Arith.Extract_Declarations (Lib_Unit); when others => |