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author | Tristan Gingold <tgingold@free.fr> | 2017-11-24 06:21:01 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-11-24 06:21:01 +0100 |
commit | 49294a83ee67eef83180721c578f69855bf96cad (patch) | |
tree | 89d3eab1be8bcc27a64340a6d69ad71a2b51adea /src/synth | |
parent | 947d5b8876198dda1cf8e0c65a554e5dbd5e80f2 (diff) | |
download | ghdl-49294a83ee67eef83180721c578f69855bf96cad.tar.gz ghdl-49294a83ee67eef83180721c578f69855bf96cad.tar.bz2 ghdl-49294a83ee67eef83180721c578f69855bf96cad.zip |
Create the simul.ads package (for a namespace).
Diffstat (limited to 'src/synth')
-rw-r--r-- | src/synth/synth-context.adb | 16 | ||||
-rw-r--r-- | src/synth/synth-context.ads | 2 | ||||
-rw-r--r-- | src/synth/synth-decls.adb | 4 | ||||
-rw-r--r-- | src/synth/synth-expr.adb | 6 | ||||
-rw-r--r-- | src/synth/synth-expr.ads | 2 | ||||
-rw-r--r-- | src/synth/synth-stmts.adb | 18 | ||||
-rw-r--r-- | src/synth/synth-types.adb | 6 | ||||
-rw-r--r-- | src/synth/synth-values.ads | 4 | ||||
-rw-r--r-- | src/synth/synthesis.adb | 4 |
9 files changed, 31 insertions, 31 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index f5dc8ad1d..975e205c5 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -23,16 +23,16 @@ with Ada.Unchecked_Deallocation; with Types; use Types; with Grt.Types; use Grt.Types; with Errorout; use Errorout; +with Iirs_Utils; -with Annotations; use Annotations; -with Execution; - -with Netlists.Builders; use Netlists.Builders; - -with Iirs_Utils; use Iirs_Utils; with Std_Package; with Ieee.Std_Logic_1164; +with Simul.Annotations; use Simul.Annotations; +with Simul.Execution; + +with Netlists.Builders; use Netlists.Builders; + with Synth.Types; use Synth.Types; with Synth.Errors; use Synth.Errors; with Synth.Expr; use Synth.Expr; @@ -97,7 +97,7 @@ package body Synth.Context is (Kind, Obj, Bounds_To_Range (Val.Bounds.D (1))); end if; if Is_Bit_Type (Get_Element_Subtype (Btype)) - and then Get_Nbr_Dimensions (Btype) = 1 + and then Iirs_Utils.Get_Nbr_Dimensions (Btype) = 1 then -- A vector of bits. return Alloc_Wire @@ -217,7 +217,7 @@ package body Synth.Context is is Slot : constant Object_Slot_Type := Get_Info (Obj).Slot; Sim_Inst : constant Block_Instance_Acc := - Execution.Get_Instance_For_Slot (Inst.Sim, Obj); + Simul.Execution.Get_Instance_For_Slot (Inst.Sim, Obj); Val : Value_Acc; begin Val := Instance_Map (Sim_Inst.Id).Objects (Slot); diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads index 52283f00d..b99179bd5 100644 --- a/src/synth/synth-context.ads +++ b/src/synth/synth-context.ads @@ -20,7 +20,7 @@ with Synth.Environment; use Synth.Environment; with Synth.Values; use Synth.Values; -with Iir_Values; use Iir_Values; +with Simul.Environments; use Simul.Environments; with Netlists; use Netlists; with Netlists.Builders; with Iirs; use Iirs; diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 65459fd7e..23e34b957 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -25,8 +25,8 @@ with Errorout; use Errorout; with Synth.Context; use Synth.Context; with Synth.Types; use Synth.Types; with Synth.Environment; use Synth.Environment; -with Iir_Values; use Iir_Values; -with Annotations; use Annotations; +with Simul.Environments; use Simul.Environments; +with Simul.Annotations; use Simul.Annotations; package body Synth.Decls is procedure Create_Var_Wire diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index fef5a18b2..00cbc0f58 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -24,7 +24,7 @@ with Std_Names; with Ieee.Std_Logic_1164; with Std_Package; with Errorout; use Errorout; -with Execution; +with Simul.Execution; with Grt.Types; use Grt.Types; with Synth.Errors; use Synth.Errors; @@ -251,7 +251,7 @@ package body Synth.Expr is Res : Value_Acc; begin -- Create bounds. - Bnd := Execution.Create_Array_Bounds_From_Type + Bnd := Simul.Execution.Create_Array_Bounds_From_Type (Syn_Inst.Sim, Aggr_Type, False); -- Allocate result Res := Create_Array_Value (Bnd.Bounds); @@ -699,7 +699,7 @@ package body Synth.Expr is | Iir_Kind_Integer_Literal | Iir_Kind_String_Literal8 => return Create_Value_Lit - (Execution.Execute_Expression (Syn_Inst.Sim, Expr), + (Simul.Execution.Execute_Expression (Syn_Inst.Sim, Expr), Get_Base_Type (Get_Type (Expr))); when Iir_Kind_Type_Conversion => return Synth_Type_Conversion (Syn_Inst, Expr); diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads index 3180b3afd..665fbc847 100644 --- a/src/synth/synth-expr.ads +++ b/src/synth/synth-expr.ads @@ -19,7 +19,7 @@ -- MA 02110-1301, USA. with Types; use Types; -with Iir_Values; use Iir_Values; +with Simul.Environments; use Simul.Environments; with Synth.Values; use Synth.Values; with Iirs; use Iirs; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 5594a6e4a..75a41d3bf 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -37,10 +37,10 @@ with Synth.Expr; use Synth.Expr; with Synth.Context; use Synth.Context; with Synth.Environment; use Synth.Environment; -with Iir_Values; use Iir_Values; -with Annotations; -with Execution; -with Elaboration; use Elaboration; +with Simul.Environments; use Simul.Environments; +with Simul.Annotations; +with Simul.Execution; +with Simul.Elaboration; use Simul.Elaboration; with Netlists; use Netlists; with Netlists.Builders; use Netlists.Builders; @@ -622,7 +622,7 @@ package body Synth.Stmts is Inter_Chain : Iir; Assoc_Chain : Iir) is - use Annotations; + use Simul.Annotations; Inter : Iir; Assoc : Iir; Assoc_Inter : Iir; @@ -648,9 +648,9 @@ package body Synth.Stmts is when Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_Variable_Declaration => -- FIXME: Arguments are passed by copy. - Elaboration.Create_Object (Subprg_Inst.Sim, Inter); + Simul.Elaboration.Create_Object (Subprg_Inst.Sim, Inter); when Iir_Kind_Interface_Signal_Declaration => - Elaboration.Create_Signal (Subprg_Inst.Sim, Inter); + Simul.Elaboration.Create_Signal (Subprg_Inst.Sim, Inter); when Iir_Kind_Interface_File_Declaration => raise Internal_Error; end case; @@ -678,7 +678,7 @@ package body Synth.Stmts is Inter_Chain : Iir; Assoc_Chain : Iir) is - use Annotations; + use Simul.Annotations; Inter : Iir; Assoc : Iir; Assoc_Inter : Iir; @@ -722,7 +722,7 @@ package body Synth.Stmts is Areapools.Mark (Syn_Inst.Sim.Marker, Instance_Pool.all); Sub_Sim_Inst := - Execution.Create_Subprogram_Instance (Syn_Inst.Sim, null, Imp); + Simul.Execution.Create_Subprogram_Instance (Syn_Inst.Sim, null, Imp); Sub_Syn_Inst := Make_Instance (Sub_Sim_Inst); Synth_Subprogram_Association diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb index 0efe3f4da..87fc1826c 100644 --- a/src/synth/synth-types.adb +++ b/src/synth/synth-types.adb @@ -23,8 +23,8 @@ with Std_Package; with Ieee.Std_Logic_1164; with Iirs_Utils; use Iirs_Utils; -with Iir_Values; use Iir_Values; -with Execution; +with Simul.Environments; use Simul.Environments; +with Simul.Execution; with Errorout; use Errorout; package body Synth.Types is @@ -62,7 +62,7 @@ package body Synth.Types is declare Bnd : Iir_Value_Literal_Acc; begin - Bnd := Execution.Execute_Bounds + Bnd := Simul.Execution.Execute_Bounds (Syn_Inst.Sim, Get_Nth_Element (Get_Index_Subtype_List (Atype), 0)); return Width (Bnd.Length); diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads index 16ead16a1..8bf58a9bc 100644 --- a/src/synth/synth-values.ads +++ b/src/synth/synth-values.ads @@ -21,7 +21,7 @@ with Types; use Types; with Netlists; use Netlists; with Synth.Environment; use Synth.Environment; -with Iir_Values; use Iir_Values; +with Simul.Environments; use Simul.Environments; with Iirs; use Iirs; package Synth.Values is @@ -63,7 +63,7 @@ package Synth.Values is W : Wire_Id; W_Range : Value_Range_Acc; when Value_Lit => - Lit : Iir_Values.Iir_Value_Literal_Acc; + Lit : Simul.Environments.Iir_Value_Literal_Acc; Lit_Type : Iir; when Value_Array => Arr : Value_Array_Acc; diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 3a4ca3c4d..a32ce2fd2 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -25,8 +25,8 @@ with Netlists.Builders; use Netlists.Builders; with Netlists.Utils; with Iirs_Utils; use Iirs_Utils; -with Iir_Values; use Iir_Values; -with Elaboration; use Elaboration; +with Simul.Environments; use Simul.Environments; +with Simul.Elaboration; use Simul.Elaboration; with Synth.Environment; use Synth.Environment; with Synth.Values; use Synth.Values; |