34 files changed, 147 insertions, 127 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 5fd84b13c..bfd7bea2d 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -31,11 +31,11 @@ with Libraries;
 with Canon;
 with Configuration;
 with Iirs_Utils;
-with Annotations;
-with Elaboration;
-with Simulation.Main;
-with Debugger;
-with Execution;
+with Simul.Annotations;
+with Simul.Elaboration;
+with Simul.Simulation.Main;
+with Simul.Debugger;
+with Simul.Execution;
 
 with Ghdlcomp;
 
@@ -60,7 +60,7 @@ package body Ghdlsimul is
       Libraries.Load_Std_Library;
 
       -- Here, time_base can be set.
-      Annotations.Annotate (Std_Package.Std_Standard_Unit);
+      Simul.Annotations.Annotate (Std_Package.Std_Standard_Unit);
 
       Canon.Canon_Flag_Add_Labels := True;
       Canon.Canon_Flag_Sequentials_Stmts := True;
@@ -115,7 +115,7 @@ package body Ghdlsimul is
 
       --  Annotate all units.
       for I in Design_Units.First .. Design_Units.Last loop
-         Annotations.Annotate (Design_Units.Table (I));
+         Simul.Annotations.Annotate (Design_Units.Table (I));
       end loop;
    end Compile_Elab;
 
@@ -136,23 +136,23 @@ package body Ghdlsimul is
       for I in Args'Range loop
          Arg := Args (I);
          if Arg.all = "--disp-tree" then
-            Simulation.Disp_Tree := True;
+            Simul.Simulation.Disp_Tree := True;
          elsif Arg.all = "--expect-failure" then
             Decode_Option (Arg.all, Status);
             pragma Assert (Status = Decode_Option_Ok);
          elsif Arg.all = "--trace-elab" then
-            Elaboration.Trace_Elaboration := True;
+            Simul.Elaboration.Trace_Elaboration := True;
          elsif Arg.all = "--trace-drivers" then
-            Elaboration.Trace_Drivers := True;
+            Simul.Elaboration.Trace_Drivers := True;
          elsif Arg.all = "--trace-simu" then
-            Simulation.Trace_Simulation := True;
+            Simul.Simulation.Trace_Simulation := True;
          elsif Arg.all = "--trace-stmt" then
-            Execution.Trace_Statements := True;
+            Simul.Execution.Trace_Statements := True;
          elsif Arg.all = "--stats" then
-            Simulation.Disp_Stats := True;
+            Simul.Simulation.Disp_Stats := True;
          elsif Arg.all = "-i" then
-            Debugger.Flag_Debugger := True;
-            Debugger.Flag_Interractive := True;
+            Simul.Debugger.Flag_Debugger := True;
+            Simul.Debugger.Flag_Interractive := True;
          else
             Decode_Option (Arg.all, Status);
             case Status is
@@ -181,7 +181,7 @@ package body Ghdlsimul is
 
       Grtlink.Flag_String := Flags.Flag_String;
 
-      Simulation.Main.Simulation_Entity (Top_Conf);
+      Simul.Simulation.Main.Simulation_Entity (Top_Conf);
 
       Set_Exit_Status (Exit_Status (Grt.Errors.Exit_Status));
    end Run;
@@ -190,7 +190,7 @@ package body Ghdlsimul is
    is
    begin
       if Option = "--debug" or Option = "-g" then
-         Debugger.Flag_Debugger := True;
+         Simul.Debugger.Flag_Debugger := True;
       else
          return False;
       end if;
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index 0ae4eff87..000e8f64a 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -25,7 +25,7 @@ with Libraries;
 with Flags;
 with Canon;
 
-with Elaboration;
+with Simul.Elaboration;
 
 with Synthesis;
 with Netlists.Dump;
@@ -95,7 +95,7 @@ package body Ghdlsynth is
 
       --  Hooks.Set_Run_Options (Args (Opt_Arg .. Args'Last));
 
-      Elaboration.Elaborate_Design (Ghdlsimul.Get_Top_Config);
+      Simul.Elaboration.Elaborate_Design (Ghdlsimul.Get_Top_Config);
 
       return Synthesis.Synth_Design (Ghdlsimul.Get_Top_Config);
       --  Hooks.Run.all;
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index f5dc8ad1d..975e205c5 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -23,16 +23,16 @@ with Ada.Unchecked_Deallocation;
 with Types; use Types;
 with Grt.Types; use Grt.Types;
 with Errorout; use Errorout;
+with Iirs_Utils;
 
-with Annotations; use Annotations;
-with Execution;
-
-with Netlists.Builders; use Netlists.Builders;
-
-with Iirs_Utils; use Iirs_Utils;
 with Std_Package;
 with Ieee.Std_Logic_1164;
 
+with Simul.Annotations; use Simul.Annotations;
+with Simul.Execution;
+
+with Netlists.Builders; use Netlists.Builders;
+
 with Synth.Types; use Synth.Types;
 with Synth.Errors; use Synth.Errors;
 with Synth.Expr; use Synth.Expr;
@@ -97,7 +97,7 @@ package body Synth.Context is
                  (Kind, Obj, Bounds_To_Range (Val.Bounds.D (1)));
             end if;
             if Is_Bit_Type (Get_Element_Subtype (Btype))
-              and then Get_Nbr_Dimensions (Btype) = 1
+              and then Iirs_Utils.Get_Nbr_Dimensions (Btype) = 1
             then
                --  A vector of bits.
                return Alloc_Wire
@@ -217,7 +217,7 @@ package body Synth.Context is
    is
       Slot : constant Object_Slot_Type := Get_Info (Obj).Slot;
       Sim_Inst : constant Block_Instance_Acc :=
-        Execution.Get_Instance_For_Slot (Inst.Sim, Obj);
+        Simul.Execution.Get_Instance_For_Slot (Inst.Sim, Obj);
       Val : Value_Acc;
    begin
       Val := Instance_Map (Sim_Inst.Id).Objects (Slot);
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 52283f00d..b99179bd5 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -20,7 +20,7 @@
 
 with Synth.Environment; use Synth.Environment;
 with Synth.Values; use Synth.Values;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Netlists; use Netlists;
 with Netlists.Builders;
 with Iirs; use Iirs;
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 65459fd7e..23e34b957 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -25,8 +25,8 @@ with Errorout; use Errorout;
 with Synth.Context; use Synth.Context;
 with Synth.Types; use Synth.Types;
 with Synth.Environment; use Synth.Environment;
-with Iir_Values; use Iir_Values;
-with Annotations; use Annotations;
+with Simul.Environments; use Simul.Environments;
+with Simul.Annotations; use Simul.Annotations;
 
 package body Synth.Decls is
    procedure Create_Var_Wire
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index fef5a18b2..00cbc0f58 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -24,7 +24,7 @@ with Std_Names;
 with Ieee.Std_Logic_1164;
 with Std_Package;
 with Errorout; use Errorout;
-with Execution;
+with Simul.Execution;
 with Grt.Types; use Grt.Types;
 
 with Synth.Errors; use Synth.Errors;
@@ -251,7 +251,7 @@ package body Synth.Expr is
                Res : Value_Acc;
             begin
                --  Create bounds.
-               Bnd := Execution.Create_Array_Bounds_From_Type
+               Bnd := Simul.Execution.Create_Array_Bounds_From_Type
                  (Syn_Inst.Sim, Aggr_Type, False);
                --  Allocate result
                Res := Create_Array_Value (Bnd.Bounds);
@@ -699,7 +699,7 @@ package body Synth.Expr is
            | Iir_Kind_Integer_Literal
            | Iir_Kind_String_Literal8 =>
             return Create_Value_Lit
-              (Execution.Execute_Expression (Syn_Inst.Sim, Expr),
+              (Simul.Execution.Execute_Expression (Syn_Inst.Sim, Expr),
                Get_Base_Type (Get_Type (Expr)));
          when Iir_Kind_Type_Conversion =>
             return Synth_Type_Conversion (Syn_Inst, Expr);
diff --git a/src/synth/synth-expr.ads b/src/synth/synth-expr.ads
index 3180b3afd..665fbc847 100644
--- a/src/synth/synth-expr.ads
+++ b/src/synth/synth-expr.ads
@@ -19,7 +19,7 @@
 --  MA 02110-1301, USA.
 
 with Types; use Types;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Synth.Values; use Synth.Values;
 with Iirs; use Iirs;
 
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 5594a6e4a..75a41d3bf 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -37,10 +37,10 @@ with Synth.Expr; use Synth.Expr;
 with Synth.Context; use Synth.Context;
 with Synth.Environment; use Synth.Environment;
 
-with Iir_Values; use Iir_Values;
-with Annotations;
-with Execution;
-with Elaboration; use Elaboration;
+with Simul.Environments; use Simul.Environments;
+with Simul.Annotations;
+with Simul.Execution;
+with Simul.Elaboration; use Simul.Elaboration;
 
 with Netlists; use Netlists;
 with Netlists.Builders; use Netlists.Builders;
@@ -622,7 +622,7 @@ package body Synth.Stmts is
       Inter_Chain : Iir;
       Assoc_Chain : Iir)
    is
-      use Annotations;
+      use Simul.Annotations;
       Inter : Iir;
       Assoc : Iir;
       Assoc_Inter : Iir;
@@ -648,9 +648,9 @@ package body Synth.Stmts is
             when Iir_Kind_Interface_Constant_Declaration
               | Iir_Kind_Interface_Variable_Declaration =>
                --  FIXME: Arguments are passed by copy.
-               Elaboration.Create_Object (Subprg_Inst.Sim, Inter);
+               Simul.Elaboration.Create_Object (Subprg_Inst.Sim, Inter);
             when Iir_Kind_Interface_Signal_Declaration =>
-               Elaboration.Create_Signal (Subprg_Inst.Sim, Inter);
+               Simul.Elaboration.Create_Signal (Subprg_Inst.Sim, Inter);
             when Iir_Kind_Interface_File_Declaration =>
                raise Internal_Error;
          end case;
@@ -678,7 +678,7 @@ package body Synth.Stmts is
       Inter_Chain : Iir;
       Assoc_Chain : Iir)
    is
-      use Annotations;
+      use Simul.Annotations;
       Inter : Iir;
       Assoc : Iir;
       Assoc_Inter : Iir;
@@ -722,7 +722,7 @@ package body Synth.Stmts is
 
       Areapools.Mark (Syn_Inst.Sim.Marker, Instance_Pool.all);
       Sub_Sim_Inst :=
-        Execution.Create_Subprogram_Instance (Syn_Inst.Sim, null, Imp);
+        Simul.Execution.Create_Subprogram_Instance (Syn_Inst.Sim, null, Imp);
       Sub_Syn_Inst := Make_Instance (Sub_Sim_Inst);
 
       Synth_Subprogram_Association
diff --git a/src/synth/synth-types.adb b/src/synth/synth-types.adb
index 0efe3f4da..87fc1826c 100644
--- a/src/synth/synth-types.adb
+++ b/src/synth/synth-types.adb
@@ -23,8 +23,8 @@ with Std_Package;
 with Ieee.Std_Logic_1164;
 with Iirs_Utils; use Iirs_Utils;
 
-with Iir_Values; use Iir_Values;
-with Execution;
+with Simul.Environments; use Simul.Environments;
+with Simul.Execution;
 with Errorout; use Errorout;
 
 package body Synth.Types is
@@ -62,7 +62,7 @@ package body Synth.Types is
                declare
                   Bnd : Iir_Value_Literal_Acc;
                begin
-                  Bnd := Execution.Execute_Bounds
+                  Bnd := Simul.Execution.Execute_Bounds
                     (Syn_Inst.Sim,
                      Get_Nth_Element (Get_Index_Subtype_List (Atype), 0));
                   return Width (Bnd.Length);
diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads
index 16ead16a1..8bf58a9bc 100644
--- a/src/synth/synth-values.ads
+++ b/src/synth/synth-values.ads
@@ -21,7 +21,7 @@
 with Types; use Types;
 with Netlists; use Netlists;
 with Synth.Environment; use Synth.Environment;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Iirs; use Iirs;
 
 package Synth.Values is
@@ -63,7 +63,7 @@ package Synth.Values is
             W : Wire_Id;
             W_Range : Value_Range_Acc;
          when Value_Lit =>
-            Lit : Iir_Values.Iir_Value_Literal_Acc;
+            Lit : Simul.Environments.Iir_Value_Literal_Acc;
             Lit_Type : Iir;
          when Value_Array =>
             Arr : Value_Array_Acc;
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index 3a4ca3c4d..a32ce2fd2 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -25,8 +25,8 @@ with Netlists.Builders; use Netlists.Builders;
 with Netlists.Utils;
 
 with Iirs_Utils; use Iirs_Utils;
-with Iir_Values; use Iir_Values;
-with Elaboration; use Elaboration;
+with Simul.Environments; use Simul.Environments;
+with Simul.Elaboration; use Simul.Elaboration;
 
 with Synth.Environment; use Synth.Environment;
 with Synth.Values; use Synth.Values;
diff --git a/src/vhdl/simulate/annotations.adb b/src/vhdl/simulate/simul-annotations.adb
index c898aa01d..de811e424 100644
--- a/src/vhdl/simulate/annotations.adb
+++ b/src/vhdl/simulate/simul-annotations.adb
@@ -22,7 +22,7 @@ with Std_Package;
 with Errorout; use Errorout;
 with Iirs_Utils; use Iirs_Utils;
 
-package body Annotations is
+package body Simul.Annotations is
    --  Current scope.  Used when an object is created to indicate which scope
    --  it belongs to.
    Current_Scope: Scope_Type := (Kind => Scope_Kind_None);
@@ -1342,4 +1342,4 @@ package body Annotations is
    begin
       return Info_Node.Table (Target);
    end Get_Info;
-end Annotations;
+end Simul.Annotations;
diff --git a/src/vhdl/simulate/annotations.ads b/src/vhdl/simulate/simul-annotations.ads
index c8519fa46..46b38d674 100644
--- a/src/vhdl/simulate/annotations.ads
+++ b/src/vhdl/simulate/simul-annotations.ads
@@ -17,10 +17,10 @@
 --  02111-1307, USA.
 
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Types; use Types;
 
-package Annotations is
+package Simul.Annotations is
    --  Decorate the tree in order to be usable with the internal simulator.
    procedure Annotate (Unit : Iir_Design_Unit);
 
@@ -117,4 +117,4 @@ package Annotations is
 
    --  For debugging.
    function Image (Scope : Scope_Type) return String;
-end Annotations;
+end Simul.Annotations;
diff --git a/src/vhdl/simulate/debugger-ams.adb b/src/vhdl/simulate/simul-debugger-ams.adb
index fec635048..2c7c86316 100644
--- a/src/vhdl/simulate/debugger-ams.adb
+++ b/src/vhdl/simulate/simul-debugger-ams.adb
@@ -20,7 +20,7 @@ with Iirs_Utils; use Iirs_Utils;
 with Ada.Text_IO; use Ada.Text_IO;
 with Disp_Vhdl;
 
-package body Debugger.AMS is
+package body Simul.Debugger.AMS is
    procedure Disp_Quantity_Name (Quantity : Quantity_Index_Type)
    is
       Obj : Scalar_Quantity renames Scalar_Quantities.Table (Quantity);
@@ -82,4 +82,4 @@ package body Debugger.AMS is
          Disp_Characteristic_Expression (I);
       end loop;
    end Disp_Characteristic_Expressions;
-end Debugger.AMS;
+end Simul.Debugger.AMS;
diff --git a/src/vhdl/simulate/debugger-ams.ads b/src/vhdl/simulate/simul-debugger-ams.ads
index f89fda276..43c094d9c 100644
--- a/src/vhdl/simulate/debugger-ams.ads
+++ b/src/vhdl/simulate/simul-debugger-ams.ads
@@ -16,13 +16,13 @@
 --  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 --  02111-1307, USA.
 
-with Elaboration.AMS; use Elaboration.AMS;
+with Simul.Elaboration.AMS; use Simul.Elaboration.AMS;
 
-package Debugger.AMS is
+package Simul.Debugger.AMS is
    procedure Disp_Quantity_Name (Quantity : Quantity_Index_Type);
 
    procedure Disp_Characteristic_Expression
      (Ce : Characteristic_Expressions_Index);
 
    procedure Disp_Characteristic_Expressions;
-end Debugger.AMS;
+end Simul.Debugger.AMS;
diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index eea71f84c..105b16e81 100644
--- a/src/vhdl/simulate/debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -32,13 +32,12 @@ with Canon;
 with Std_Names;
 with Libraries;
 with Std_Package;
-with Annotations; use Annotations;
-with Elaboration; use Elaboration;
+with Simul.Annotations; use Simul.Annotations;
+with Simul.Elaboration; use Simul.Elaboration;
 with Iirs_Utils; use Iirs_Utils;
 with Errorout; use Errorout;
 with Disp_Vhdl;
-with Execution; use Execution;
---with Simulation; use Simulation;
+with Simul.Execution; use Simul.Execution;
 with Iirs_Walk; use Iirs_Walk;
 with Areapools; use Areapools;
 with Grt.Types;
@@ -47,7 +46,7 @@ with Grt.Readline;
 with Grt.Errors;
 with Grt.Disp_Signals;
 
-package body Debugger is
+package body Simul.Debugger is
    --  This exception can be raised by a debugger command to directly return
    --  to the prompt.
    Command_Error : exception;
@@ -2281,4 +2280,4 @@ package body Debugger is
    begin
       Debug (Reason_Error);
    end Debug_Error;
-end Debugger;
+end Simul.Debugger;
diff --git a/src/vhdl/simulate/debugger.ads b/src/vhdl/simulate/simul-debugger.ads
index ecb170eaa..9deba556b 100644
--- a/src/vhdl/simulate/debugger.ads
+++ b/src/vhdl/simulate/simul-debugger.ads
@@ -17,9 +17,9 @@
 --  02111-1307, USA.
 
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 
-package Debugger is
+package Simul.Debugger is
    Flag_Debugger : Boolean := False;
    Flag_Interractive : Boolean := False;
 
@@ -88,4 +88,4 @@ package Debugger is
 
    --  Call the debugger in case of error.
    procedure Debug_Error;
-end Debugger;
+end Simul.Debugger;
diff --git a/src/vhdl/simulate/elaboration-ams.adb b/src/vhdl/simulate/simul-elaboration-ams.adb
index de4edc980..f5cf20110 100644
--- a/src/vhdl/simulate/elaboration-ams.adb
+++ b/src/vhdl/simulate/simul-elaboration-ams.adb
@@ -17,9 +17,9 @@
 --  02111-1307, USA.
 
 with Errorout; use Errorout;
-with Execution;
+with Simul.Execution;
 
-package body Elaboration.AMS is
+package body Simul.Elaboration.AMS is
    function Create_Characteristic_Expression
      (Kind : Characteristic_Expr_Kind) return Characteristic_Expressions_Index
    is
@@ -196,4 +196,4 @@ package body Elaboration.AMS is
          Compute_Dependencies (I);
       end loop;
    end Create_Tables;
-end Elaboration.AMS;
+end Simul.Elaboration.AMS;
diff --git a/src/vhdl/simulate/elaboration-ams.ads b/src/vhdl/simulate/simul-elaboration-ams.ads
index f4c295a97..f7f063019 100644
--- a/src/vhdl/simulate/elaboration-ams.ads
+++ b/src/vhdl/simulate/simul-elaboration-ams.ads
@@ -18,7 +18,7 @@
 
 with Tables;
 
-package Elaboration.AMS is
+package Simul.Elaboration.AMS is
    --  AMS expressions
    --
    --  At many places during elaboration, the LRM defines characteristic
@@ -160,4 +160,4 @@ package Elaboration.AMS is
       Table_Component_Type => Scalar_Quantity,
       Table_Low_Bound => 1,
       Table_Initial => 128);
-end Elaboration.AMS;
+end Simul.Elaboration.AMS;
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index a2700cb6b..86a936458 100644
--- a/src/vhdl/simulate/elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -20,18 +20,18 @@ with Ada.Text_IO;
 with Str_Table;
 with Errorout; use Errorout;
 with Evaluation;
-with Execution; use Execution;
+with Simul.Execution; use Simul.Execution;
 with Iirs_Utils; use Iirs_Utils;
 with Libraries;
 with Name_Table;
-with File_Operation;
+with Simul.File_Operation;
 with Iir_Chains; use Iir_Chains;
-with Elaboration.AMS; use Elaboration.AMS;
+with Simul.Elaboration.AMS; use Simul.Elaboration.AMS;
 with Areapools; use Areapools;
 with Grt.Errors;
 with Grt.Options;
 
-package body Elaboration is
+package body Simul.Elaboration is
 
    procedure Elaborate_Dependence (Design_Unit: Iir_Design_Unit);
 
@@ -2976,4 +2976,4 @@ package body Elaboration is
       pragma Assert (Is_Empty (Expr_Pool));
    end Elaborate_Design;
 
-end Elaboration;
+end Simul.Elaboration;
diff --git a/src/vhdl/simulate/elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads
index 6bbb91cc1..07969719f 100644
--- a/src/vhdl/simulate/elaboration.ads
+++ b/src/vhdl/simulate/simul-elaboration.ads
@@ -19,13 +19,13 @@
 with Tables;
 with Types; use Types;
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Grt.Types; use Grt.Types;
-with Annotations; use Annotations;
+with Simul.Annotations; use Simul.Annotations;
 
 --  This package elaborates design hierarchy.
 
-package Elaboration is
+package Simul.Elaboration is
    Trace_Elaboration : Boolean := False;
    Trace_Drivers : Boolean := False;
 
@@ -184,4 +184,4 @@ package Elaboration is
       Table_Index_Type => PSL_Index_Type,
       Table_Low_Bound => 1,
       Table_Initial => 2);
-end Elaboration;
+end Simul.Elaboration;
diff --git a/src/vhdl/simulate/iir_values.adb b/src/vhdl/simulate/simul-environments.adb
index 62b70f9c2..16f9bc3f0 100644
--- a/src/vhdl/simulate/iir_values.adb
+++ b/src/vhdl/simulate/simul-environments.adb
@@ -20,9 +20,9 @@ with System;
 with Ada.Unchecked_Conversion;
 with GNAT.Debug_Utilities;
 with Name_Table;
-with Debugger; use Debugger;
+with Simul.Debugger; use Simul.Debugger;
 
-package body Iir_Values is
+package body Simul.Environments is
 
    -- Functions for iir_value_literal
    function Is_Equal (Left, Right: Iir_Value_Literal_Acc) return Boolean is
@@ -1124,4 +1124,4 @@ package body Iir_Values is
             Put ("[environment]");
       end case;
    end Disp_Iir_Value;
-end Iir_Values;
+end Simul.Environments;
diff --git a/src/vhdl/simulate/iir_values.ads b/src/vhdl/simulate/simul-environments.ads
index 68b6d1326..e043659b3 100644
--- a/src/vhdl/simulate/iir_values.ads
+++ b/src/vhdl/simulate/simul-environments.ads
@@ -26,7 +26,7 @@ with Grt.Files;
 with Areapools; use Areapools;
 -- with System.Debug_Pools;
 
-package Iir_Values is
+package Simul.Environments is
    -- During simulation, all values are contained into objects of type
    -- iir_value_literal.  The annotation pass creates such objects for every
    -- literal of units.  The elaboration pass creates such objects for
@@ -478,4 +478,4 @@ package Iir_Values is
 
    -- Disp a value_literal in readable form.
    procedure Disp_Iir_Value (Value: Iir_Value_Literal_Acc; A_Type: Iir);
-end Iir_Values;
+end Simul.Environments;
diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/simul-execution.adb
index dc4792490..d6639c06d 100644
--- a/src/vhdl/simulate/execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -25,20 +25,20 @@ with Errorout; use Errorout;
 with Std_Package;
 with Evaluation;
 with Iirs_Utils; use Iirs_Utils;
-with Annotations; use Annotations;
+with Simul.Annotations; use Simul.Annotations;
 with Name_Table;
-with File_Operation;
-with Debugger; use Debugger;
+with Simul.File_Operation;
+with Simul.Debugger; use Simul.Debugger;
 with Std_Names;
 with Str_Table;
 with Files_Map;
 with Iir_Chains; use Iir_Chains;
-with Simulation; use Simulation;
+with Simul.Simulation; use Simul.Simulation;
 with Grt.Astdio;
 with Grt.Stdio;
 with Grt.Options;
 with Grt.Vstrings;
-with Grt_Interface;
+with Simul.Grt_Interface;
 with Grt.Values;
 with Grt.Errors;
 with Grt.Std_Logic_1164;
@@ -46,7 +46,7 @@ with Grt.Lib;
 with Grt.Strings;
 with Sem_Inst;
 
-package body Execution is
+package body Simul.Execution is
 
    function Execute_Function_Call
      (Block: Block_Instance_Acc; Expr: Iir; Imp : Iir)
@@ -4828,4 +4828,4 @@ package body Execution is
          end case;
       end loop;
    end Execute_Sequential_Statements;
-end Execution;
+end Simul.Execution;
diff --git a/src/vhdl/simulate/execution.ads b/src/vhdl/simulate/simul-execution.ads
index d9406be94..358c26eae 100644
--- a/src/vhdl/simulate/execution.ads
+++ b/src/vhdl/simulate/simul-execution.ads
@@ -18,11 +18,11 @@
 
 with Types; use Types;
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
-with Elaboration; use Elaboration;
+with Simul.Environments; use Simul.Environments;
+with Simul.Elaboration; use Simul.Elaboration;
 with Areapools; use Areapools;
 
-package Execution is
+package Simul.Execution is
    Trace_Statements : Boolean := False;
 
    -- If true, disp current time in assert message.
@@ -189,4 +189,4 @@ package Execution is
    function Execute_Image_Attribute (Val : Iir_Value_Literal_Acc;
                                      Expr_Type : Iir)
                                     return String;
-end Execution;
+end Simul.Execution;
diff --git a/src/vhdl/simulate/file_operation.adb b/src/vhdl/simulate/simul-file_operation.adb
index dab6ec889..98b1729c2 100644
--- a/src/vhdl/simulate/file_operation.adb
+++ b/src/vhdl/simulate/simul-file_operation.adb
@@ -17,13 +17,13 @@
 --  02111-1307, USA.
 
 with Types; use Types;
-with Annotations; use Annotations;
-with Execution; use Execution;
-with Debugger; use Debugger;
-with Grt_Interface; use Grt_Interface;
+with Simul.Annotations; use Simul.Annotations;
+with Simul.Execution; use Simul.Execution;
+with Simul.Debugger; use Simul.Debugger;
+with Simul.Grt_Interface; use Simul.Grt_Interface;
 with Grt.Lib;
 
-package body File_Operation is
+package body Simul.File_Operation is
    --  Open a file.
    --  See LRM93 3.4.1 for definition of arguments.
    --  IS_TEXT is true if the file format is text.
@@ -381,4 +381,4 @@ package body File_Operation is
       end loop;
       return Grt.Lib.Textio_Read_Real (Str_Arg'Unrestricted_Access);
    end Textio_Read_Real;
-end File_Operation;
+end Simul.File_Operation;
diff --git a/src/vhdl/simulate/file_operation.ads b/src/vhdl/simulate/simul-file_operation.ads
index ef3b8b22b..5844cea77 100644
--- a/src/vhdl/simulate/file_operation.ads
+++ b/src/vhdl/simulate/simul-file_operation.ads
@@ -17,11 +17,11 @@
 --  02111-1307, USA.
 
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 with Grt.Files; use Grt.Files;
 with Grt.Types; use Grt.Types;
 
-package File_Operation is
+package Simul.File_Operation is
    Null_File : constant Natural := 0;
 
    --  Open a file.
@@ -86,4 +86,4 @@ package File_Operation is
                                 Ndigits : Std_Integer);
 
    function Textio_Read_Real (Str : Iir_Value_Literal_Acc) return Ghdl_F64;
-end File_Operation;
+end Simul.File_Operation;
diff --git a/src/vhdl/simulate/grt_interface.adb b/src/vhdl/simulate/simul-grt_interface.adb
index 604d30d01..a8ff0a056 100644
--- a/src/vhdl/simulate/grt_interface.adb
+++ b/src/vhdl/simulate/simul-grt_interface.adb
@@ -19,7 +19,7 @@
 with Iirs; use Iirs;
 with Types; use Types;
 
-package body Grt_Interface is
+package body Simul.Grt_Interface is
    To_Dir : constant array (Iir_Direction) of Ghdl_Dir_Type :=
      (Iir_To => Dir_To, Iir_Downto => Dir_Downto);
 
@@ -41,4 +41,4 @@ package body Grt_Interface is
            Character'Val (Val.Val_Array.V (I).E8);
       end loop;
    end Set_Std_String_From_Iir_Value;
-end Grt_Interface;
+end Simul.Grt_Interface;
diff --git a/src/vhdl/simulate/grt_interface.ads b/src/vhdl/simulate/simul-grt_interface.ads
index 05f7abb69..6ce89fe7f 100644
--- a/src/vhdl/simulate/grt_interface.ads
+++ b/src/vhdl/simulate/simul-grt_interface.ads
@@ -17,11 +17,11 @@
 --  02111-1307, USA.
 
 with Grt.Types; use Grt.Types;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 
-package Grt_Interface is
+package Simul.Grt_Interface is
    procedure Set_Std_String_From_Iir_Value (Str : Std_String;
                                             Val : Iir_Value_Literal_Acc);
 
    function Build_Bound (Arr : Iir_Value_Literal_Acc) return Std_String_Bound;
-end Grt_Interface;
+end Simul.Grt_Interface;
diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 7c68d0b68..4614b2746 100644
--- a/src/vhdl/simulate/simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -25,19 +25,19 @@ with PSL.Nodes;
 with PSL.NFAs;
 with Std_Package;
 with Trans_Analyzes;
-with Elaboration; use Elaboration;
-with Execution; use Execution;
+with Simul.Elaboration; use Simul.Elaboration;
+with Simul.Execution; use Simul.Execution;
 with Ieee.Std_Logic_1164;
 with Grt.Main;
-with Debugger; use Debugger;
-with Debugger.AMS;
+with Simul.Debugger; use Simul.Debugger;
+with Simul.Debugger.AMS;
 with Grt.Errors;
 with Grt.Rtis;
 with Grt.Processes;
 with Grt.Signals;
 with Areapools; use Areapools;
 
-package body Simulation.Main is
+package body Simul.Simulation.Main is
    --  Configuration for the whole design
    Top_Config : Iir_Design_Unit;
 
@@ -1142,4 +1142,4 @@ package body Simulation.Main is
       when Simulation_Finished =>
          null;
    end Simulation_Entity;
-end Simulation.Main;
+end Simul.Simulation.Main;
diff --git a/src/vhdl/simulate/simulation-main.ads b/src/vhdl/simulate/simul-simulation-main.ads
index ed8fe5d69..28ed8ca08 100644
--- a/src/vhdl/simulate/simulation-main.ads
+++ b/src/vhdl/simulate/simul-simulation-main.ads
@@ -1,4 +1,4 @@
-package Simulation.Main is
+package Simul.Simulation.Main is
    --  The entry point of the simulator.
    procedure Simulation_Entity (Top_Conf : Iir_Design_Unit);
-end Simulation.Main;
+end Simul.Simulation.Main;
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simul-simulation.adb
index 0d23a20f8..cc8c4aa51 100644
--- a/src/vhdl/simulate/simulation.adb
+++ b/src/vhdl/simulate/simul-simulation.adb
@@ -17,14 +17,14 @@
 --  02111-1307, USA.
 
 with Types; use Types;
-with Execution; use Execution;
+with Simul.Execution; use Simul.Execution;
 with Areapools; use Areapools;
 with Grt.Signals;
 with Grt.Processes;
 with Grtlink;
 pragma Unreferenced (Grtlink);
 
-package body Simulation is
+package body Simul.Simulation is
 
    function Value_To_Iir_Value (Mode : Mode_Type; Val : Value_Union)
                                return Iir_Value_Literal_Acc is
@@ -713,4 +713,4 @@ package body Simulation is
 
       return Ghdl_B1'Val (Boolean'Pos (Val));
    end Guard_Func;
-end Simulation;
+end Simul.Simulation;
diff --git a/src/vhdl/simulate/simulation.ads b/src/vhdl/simulate/simul-simulation.ads
index fa3a54982..5ab01a6ff 100644
--- a/src/vhdl/simulate/simulation.ads
+++ b/src/vhdl/simulate/simul-simulation.ads
@@ -19,9 +19,9 @@
 with System;
 with Grt.Types; use Grt.Types;
 with Iirs; use Iirs;
-with Iir_Values; use Iir_Values;
+with Simul.Environments; use Simul.Environments;
 
-package Simulation is
+package Simul.Simulation is
    Trace_Simulation : Boolean := False;
    Disp_Tree : Boolean := False;
    Disp_Stats : Boolean := False;
@@ -133,4 +133,4 @@ private
    procedure Execute_Write_Signal (Sig: Iir_Value_Literal_Acc;
                                    Val : Iir_Value_Literal_Acc;
                                    Attr : Write_Signal_Enum);
-end Simulation;
+end Simul.Simulation;
diff --git a/src/vhdl/simulate/simul.ads b/src/vhdl/simulate/simul.ads
new file mode 100644
index 000000000..6685959c5
--- /dev/null
+++ b/src/vhdl/simulate/simul.ads
@@ -0,0 +1,21 @@
+--  Interpreted simulation base package.
+--  Copyright (C) 2017 Tristan Gingold
+--
+--  GHDL is free software; you can redistribute it and/or modify it under
+--  the terms of the GNU General Public License as published by the Free
+--  Software Foundation; either version 2, or (at your option) any later
+--  version.
+--
+--  GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
+--  WARRANTY; without even the implied warranty of MERCHANTABILITY or
+--  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+--  for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with GHDL; see the file COPYING.  If not, write to the Free
+--  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+--  02111-1307, USA.
+
+package Simul is
+   pragma Pure (Simul);
+end Simul;