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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-18 21:32:59 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-20 21:54:35 +0100 |
| commit | 418800b56e3296eec94e56707ebad7dcd1d1c6ee (patch) | |
| tree | 3dc316321d3bdef39629dc57dde9651e276b9f2b /src/synth | |
| parent | a53b01b53c3c8225a832e8f20d019ac39d68ce38 (diff) | |
| download | ghdl-418800b56e3296eec94e56707ebad7dcd1d1c6ee.tar.gz ghdl-418800b56e3296eec94e56707ebad7dcd1d1c6ee.tar.bz2 ghdl-418800b56e3296eec94e56707ebad7dcd1d1c6ee.zip | |
synth: create sub-instace for processes
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_annotations.adb | 6 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_context.adb | 10 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_context.ads | 5 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_stmts.adb | 2 |
4 files changed, 17 insertions, 6 deletions
diff --git a/src/synth/elab-vhdl_annotations.adb b/src/synth/elab-vhdl_annotations.adb index 0d7af8c79..3a076cde2 100644 --- a/src/synth/elab-vhdl_annotations.adb +++ b/src/synth/elab-vhdl_annotations.adb @@ -983,13 +983,9 @@ package body Elab.Vhdl_Annotations is procedure Annotate_Process_Statement (Block_Info : Sim_Info_Acc; Stmt : Iir) is - pragma Unreferenced (Block_Info); Info : Sim_Info_Acc; begin - Info := new Sim_Info_Type'(Kind => Kind_Process, - Ref => Stmt, - Nbr_Objects => 0); - Set_Ann (Stmt, Info); + Info := Create_Block_Info (Block_Info, Stmt); Annotate_Declaration_List (Info, Get_Declaration_Chain (Stmt)); diff --git a/src/synth/elab-vhdl_context.adb b/src/synth/elab-vhdl_context.adb index 99f3efb1d..7b905f663 100644 --- a/src/synth/elab-vhdl_context.adb +++ b/src/synth/elab-vhdl_context.adb @@ -484,6 +484,16 @@ package body Elab.Vhdl_Context is return Syn_Inst.Objects (Info.Inst_Slot).I_Inst; end Get_Sub_Instance; + procedure Set_Sub_Instance (Syn_Inst : Synth_Instance_Acc; + Stmt : Node; + Sub_Inst : Synth_Instance_Acc) + is + Info : constant Sim_Info_Acc := Get_Ann (Stmt); + begin + pragma Assert (Syn_Inst.Objects (Info.Inst_Slot).I_Inst = null); + Syn_Inst.Objects (Info.Inst_Slot).I_Inst := Sub_Inst; + end Set_Sub_Instance; + function Get_Component_Instance (Syn_Inst : Synth_Instance_Acc) return Synth_Instance_Acc is diff --git a/src/synth/elab-vhdl_context.ads b/src/synth/elab-vhdl_context.ads index 13fe8bb49..69435d283 100644 --- a/src/synth/elab-vhdl_context.ads +++ b/src/synth/elab-vhdl_context.ads @@ -194,6 +194,11 @@ package Elab.Vhdl_Context is function Get_Component_Instance (Syn_Inst : Synth_Instance_Acc) return Synth_Instance_Acc; + -- For processes, whose instance is not set during elaboration. + procedure Set_Sub_Instance (Syn_Inst : Synth_Instance_Acc; + Stmt : Node; + Sub_Inst : Synth_Instance_Acc); + -- Return the scope of BLK. Deals with architecture bodies. function Get_Info_Scope (Blk : Node) return Sim_Info_Acc; diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb index 6f0339534..ebb2380b2 100644 --- a/src/synth/elab-vhdl_stmts.adb +++ b/src/synth/elab-vhdl_stmts.adb @@ -268,7 +268,7 @@ package body Elab.Vhdl_Stmts is begin case Get_Kind (Stmt) is when Iir_Kinds_Process_Statement => - null; + Create_Sub_Instance (Syn_Inst, Stmt, null); when Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment |